LTC1694 Просмотр технического описания (PDF) - Linear Technology

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LTC1694

SMBus/I2C Accelerator

Linear Technology 

LTC1694

APPLICATIO S I FOR ATIO

ACK Data Setup Time

The data setup time requirement for ACK (acknowledge)

must be fulfilled if a high value of RS is used. An acknowl-

edge is accomplished by the SMBus host releasing the

SDA line (pulling high) at the end of the last bit sent and the

SMBus slave device pulling the SDA line low before the

rising edge of the ACK clock pulse.

The LTC1694 2.2mA boosted pull-up current is activated

when the SMBus host releases the SDA line, allowing the

voltage to rise above the LTC1694’s comparator threshold

of 0.65V. If an SMBus slave device has a high value of RS,

a longer time is required for this SMBus slave device to pull

SDA low before the rising edge of the ACK clock pulse.

To ensure sufficient data setup time for ACK, SMBus slave

devices, with high values of RS, should pull the SDA low

earlier. Typically, a minimum setup time of 1.5µs is needed

for an SMBus device with an RS of 700Ω and a bus

capacitance of 200pF.

An alternative is that the SMBus slave device can hold SCL

line low until the SDA line reaches a stable state. Then, SCL

can be released to generate the ACK clock pulse.

PACKAGE DESCRIPTIO

0.62

0.95

MAX

REF

S5 Package

5-Lead Plastic TSOT-23

(Reference LTC DWG # 05-08-1635)

1.22 REF

2.90 BSC

(NOTE 4)

3.85 MAX 2.62 REF

1.4 MIN

2.80 BSC

1.50 – 1.75

(NOTE 4)

RECOMMENDED SOLDER PAD LAYOUT

PER IPC CALCULATOR

0.20 BSC

DATUM ‘A’

0.30 – 0.50 REF

0.09 – 0.20

NOTE:

(NOTE 3)

1. DIMENSIONS ARE IN MILLIMETERS

2. DRAWING NOT TO SCALE

3. DIMENSIONS ARE INCLUSIVE OF PLATING

4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR

5. MOLD FLASH SHALL NOT EXCEED 0.254mm

6. JEDEC PACKAGE REFERENCE IS MO-193

PIN ONE

0.95 BSC

0.80 – 0.90

1.00 MAX

1.90 BSC

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

0.30 – 0.45 TYP

5 PLCS (NOTE 3)

0.01 – 0.10

S5 TSOT-23 0302

1694fa

7

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