CDP1020 Просмотр технического описания (PDF) - Intersil
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CDP1020 Datasheet PDF : 23 Pages
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CDP1020
Solenoid Drivers
For control of the device bay software controlled solenoids,
the SFTLOCK pins have drive capability to gate an external,
solenoid control MOSFET. Typical circuit configuration is
shown in Figure 18. Note that since the output voltage is not
charge-pumped, only the VDD voltage (3.3V to 5V) is
available to drive a FET input gate; therefore, a logic level
FET such as the Intersil HUF76113DK8 is recommended.
PIIX4 SOUTH BRIDGE
SYSTEM RESET
+3.3V (AUX)
+3.3V (AUX)
3.3kΩ
100PF
+5V (MAIN)
+12V
+3.3V (AUX)
14
2
24
VGATE TEST VDD
11
SDA
12
SCK
13
ALRT
1394PR0 3
4
USBPR0
15
PWREN0
+3.3V
A8
A10
HUF76113DK8 (1/2)
VID
A13
1
RESET
26
CLK
23 VLED
5
REMREQ0
17
SFTLOCK0
6
SECURE0
+12V
27
AD0
28
AD1
CDP1020
19
LEDG0
LEDA0 20
VSS
25
180Ω
BAY STATUS LED
2 COLOR,
COMMON CATHODE
REMOVE REQUEST
(N.O.)
BAY LOCK
SOLENOID
BAY SECURITY
LOCK/SWITCH
FIGURE 18. TYPICAL CDP1020 SYSTEM HARDWARE CONNECTIONS - PiiX4 BASED INTEL ARCHITECTURE PLATFORM (ONLY BAY
0 SHOWN)
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out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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