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L6353

SMART DRIVER FOR POWER MOS & IGBT

STMicroelectronics 

Figure 4. Gate driving waveforms test circuit.

L6353

POSITIVE

SUPPLY

SELECT

VH.V.

100µF-35V

VCC

VPOS

DFW

ON_SENSE

LOAD

100nF

INPUT

100nF

Vin

VREF

CLAMP_PROG

LOGIC

MON DELAY

DELAY

ON_LEV_PROG

OUT1

VG

VCE

1.2Ω

OUT2

COM 5.6Ω

VSS(**)

NEGATIVE

100µF-10V SUPPLY

12KΩ

VREF

2.2KΩ

100nF

(*)

47KΩ

VREF

1nF

4.7KΩ

VREF

100pF

12KΩ

VREF

12KΩ

100nF

(*)

D94IN116B

NOTES:

(*) The capacitor is required if the pin is left floating.

(**) If the negative supply is not used, the VSS pin must be connected to the COM pin as close as possible to the IC.

INPUT INTERFACE

To drive the external power device three different

possibilities are allowed:

The Logic Level Mode, either direct or inverted,

and the Pulse Transformer Mode

Using the Logic Level Mode (direct) an high level

(referred to COM), at the INPUT pin will start the

Turn on Procedure (i.e. firing an N channel exter-

nal device). A low level (referred to COM) will in-

stead close the OUT2 pin to VSS.

The functioning is reversed in the inverted mode.

To select the direct mode the SELECT pin must

be connected via a capacitor to COM. The in-

verted mode is chosen by connecting the SE-

LECT pin to COM.

In logic Level Mode pulses lasting less than tinh

(200ns typ.) are filtered out.

In the Pulse Transformer Mode the SELECT pin

will be the reference pin for the signal applied to

the INPUTpin. The positive pulse will start the

TURN ON PROCEDURE, while the negative

pulse will close OUT2 to VSS. The duration of this

pulses (tw, see fig.2) must be again tw > tinh.

TURN-ON PROCEDURE

The firing of the external power device is per-

formed in three steps in order to avoid the most

common problems that can arise.

In each of these steps there are a number of pa-

rameters that can be easily externally presetted to

the requested values.

First Step

Parameter: tDELAY

In order to avoid cross-conduction between the

external power device in half bridge arrangement

the driver output is activated after an externally

programmable delay time (tDELAY, see fig. 3) after

the input signal. To set the tDELAYinterval an R-C

network has to be connected between the DE-

LAY, VREF and COM pins (see fig.4) giving:

tDELAY (µsec) = REXT (KΩ) . CEXT(nF)+ ton

To minimize this interval only a resistor has to be

connected between the DELAY and the VREF lim-

iting thus the duration to the internal propagation

delay ton.

Second step

Parameters: tMON_DELAY, VCL

To protect the driven device from latch-up at turn-

on (IGBT) after the tDELAY time interval a second

externally programmable time interval tMON_DE-

LAY (presettable using the same technique used

to set the tDELAY interval, see fig.4)

tMON-DELAY (µsec) = REXT (KΩ) . CEXT(nF)

during the tMON_DELAY the voltage on the VOUT1)

is limited to the VCL level. To program this value

an appropriate voltage drop has to be imposed,

by mean of a resistive voltage divider, at the

CLAMP_PROG pin according to the following for-

mula:

7/11

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