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MX98726EC

SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE

Macronix International 

MX98726EC

3.0 Register (Default value is defined after hardware/power-up reset)

Reset logic : All register bits are cleared by hardware reset, while register bit with an "*" in its symbol

name is also cleared by software reset.

Network Control Register A : NCRA (Reg00h),R/W, default=00h

Bit

Symbol

Description

0.0

RESET

Software reset.

0.1

ST0*

Start Transmit Command/Status : Write to issue commands. When done, both bits are

0.2

ST1*

cleared automatically.

Transmit command : ST1 ST0

IDLE state

0 0 Read to indicate TX DMA idle state, write has no effect.

TX DMA Poll

0 1 Start TX DMA, send packets stored in packet memory.

TX FIFO Send

1 0 Immediately send the packet stored in the TX FIFO.

TX DMA Poll

1 1 Start TX DMA, send packets stored in packet memory.

0.3

0.4, 0.5

SR*

LB0*,LB1*

All transmit commands are cleared to 00 when the operation is done to indicate idle

state. When the TX DMA poll and the TX FIFO Send can not be used at the same time.

New packet can be written to the FIFO directly only when ST1, ST0=IDLE and

TXDMA[3:0]=1h. The TX DMA poll and the TX FIFO Send commands can be issued only

when ST1, ST0=IDLE and TXDMA[3:0]=1h, regardless of any error status in previous

transmission.

Start Receive: Enable the MAC receive packets. Default is disabled.

Loopback Mode: LB1 LB0

Mode0

0

0

Normal mode

Mode1

0

1

Internal FIFO Loopback

Mode2

1

0

Internal NWAY Loopback

Mode3

1

1

Internal PMD Loopback

Mode 2 and 3 are reserved for IC test purpose. Only mode 1 can be used on bench.

External loopback for bench can be done by full duplex normal mode with real cable

hooked up from TX port to RX port.

0.6

INTMODE Interrupt Mode: Set for active high interrupt, reset for active low interrupt case.

0.7

CLKSEL Clock Select : Set to use internal 40MHz clock for all internal DMA, default is reset to use

internal 50MHz clock for all internal DMA.

P/N:PM0729

REV. 1.1, MAY. 28, 2001

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