MX98726EC Просмотр технического описания (PDF) - Macronix International

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MX98726EC

SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE

Macronix International 

1.2 Internal Block Diagram

MX98726EC

Host

Packet Buffer

(SRAM)

EPROM

SRAMIU

Serial ROM port

BIU

RX

FIFO

TX

FIFO

RX

TX

SM

SM

PCS

100 TX PHY

100TX PMD

interface

NWAY

CTRL & REGS

10Mbps

MCC+TP interface

MII Interface

Architecture and Interface overview

1.3 Typical Applications

Packet

buffer

EPROM

C46/C66

local DMA

uP with dedicate bus

Host side

CSB

MX98726EC

RJ45 TP cable

Xformer

decode

Customer Application

P/N:PM0729

Interleaved memory Architecture

2

REV. 1.1, MAY. 28, 2001

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