HPMX-2003-T10 Просмотр технического описания (PDF) - HP => Agilent Technologies

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HPMX-2003-T10

Silicon Bipolar RFIC 900 MHz Vector Modulator

HP => Agilent Technologies 

HPMX-2003 JDC

Applications

The JDC System

JDC (Japan Digital Cellular) com-

monly refers to the Japanese digi-

tal cellular telephone system

standard. Digital cellular phones

for the Japanese market must

conform to this standard. The JDC

system is characterized by 25 kHz

channel spacing and mobile to

base transmit frequencies of 940 –

960 MHz. The primary modulation

characteristics include π/4 DQPSK

filtering of the I and Q signals and

42 kbps transmission rate.

Critical Performance

Parameters

JDC standards require that the

telephone exhibit RMS modula-

tion error ≤ 12.5%. The modulated

output spectrum of the phone

must lie within a “spectral mask”

which defines maximum allow-

able radiation levels into adjacent

and alternate channels. Specifi-

cally, 50 kHz from the channel

center frequency (f0), the output

of the phone must be at least

45␣ dB below the peak output at f 0.

100 kHz from f0, the output must

be at least 60 dB below the peak

output at f0. Refer to the JDC

specifications for more detailed

information.

HPMX-2003 Performance

The typical RMS modulation error

level of 4% makes the HPMX-2003

an excellent choice for JDC appli-

cations. The output spectrum falls

easily within the JDC spectral

mask, and the high power and

simple output configuration mean

lower components count, reduced

size and higher system efficiency.

Particulars of Use

Many of the JDC application per-

formance graphs shown in this

data sheet were created using the

test board shown in figure 41,be-

low.

The only external components

required by this IC are four chip

capacitors. One capacitor is used

as a DC block on the input trans-

mission line. The second capaci-

tor (at pin 8) provides an AC

ground to one side of the differen-

tial LO input. The third and fourth

capacitors (at pins 1 and 16) are

for VCC bypass.

The circuit board includes an in-

ductive trace that can optionally

be used to minimize output VSWR

by placing a bypass capacitor at

various points along the inductive

line. Minimum VSWR for JDC

applications is achieved by plac-

ing the capacitor as shown in the

circle (inductance ≈ 0 nH).

The IC has an internal blocking

capacitor so the output is a simple

50 Ω transmission line. An en-

larged scale layout of this board

can be found on the last page of

this data sheet.

VER. 1

C

C

LO

Q

C

C

OUT

R

VCC

5V

I

R

Figure 41. HPMX-2003 JDC Test Board.

7-51

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