CXA2079Q Просмотр технического описания (PDF) - Sony Semiconductor
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CXA2079Q Datasheet PDF : 20 Pages
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I2C BUS Control Signal
CXA2079Q
34 SDA
33 SCL
tBUF
tLOW
tHD;STA
tR
tHD;DAT
tHIGH tF
tSU;DAT
tSU;STA
P
S
S
Fig. 6. I2C BUS Control Signal Timing Chart
tSU;STO
P
Description of Operation
The CXA2079Q is a TV I2C bus-compatible AV switch IC. The video system and the stereo audio system both
have 6 inputs and 2 outputs each. 4 of the 6 video system inputs support S2 and S protocols.
The desired inputs can be independently assigned to each output (in the audio system, the left and right
channels are processed as one unit) by I2C bus control. However, the same input is assigned to both the video
and audio system output 2.
I2C BUS Registers
1) I2C BUS
The I2C bus (inter-IC bus) is an inter-IC bus system developed by Philips. Two lines (SDA – serial data, SCL –
serial clock) provide control over start, stop, data transfer, synchronization, and collision avoidance. The IC
outputs are either open collector or open drain, forming a bus line in the wired OR format.
SDA
A
A
MSB
LSB
MSB
LSB
SCL
S
1 234 567 891 2
S: Start condition; SDA is set "Low" when SCL is "High"
P: Stop condition; SDA is set "High" when SCL is "High"
A: Acknowledge; signal sent from the slave
P
9
Data is transmitted by MSB-first. One data unit consists of 8 bits, to which the acknowledge signal, which
indicates that the data has been accepted by the slave, is attached at the end. Normally, the slave∗1 IC
receives data at the rising edge of SCL and the master∗2 IC changes data at the falling edge of SCL.
∗1 Slave: An IC that is placed under the control of the master. In a normal system, all devices excluding the
central microcomputer are slaves.
∗2 Master: A central microcomputer or other controlling IC.
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