HS-80C86RH(1995) Просмотр технического описания (PDF) - Intersil
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HS-80C86RH Datasheet PDF : 37 Pages
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HS-80C86RH
Pin Description (Continued)
SYMBOL
PIN
NUMBER TYPE
DESCRIPTION
LOCK
29
O
LOCK: output indicates that other system bus masters are not to gain control of the system bus
while LOCK is active LOW. The LOCK signal is activated by the “LOCK” prefix instruction and re-
mains active until the completion of the next instruction. This signal is active LOW, and is held at a
HIGH impedance logic one state during “grant sequence”. In MAX mode, LOCK is automatically
generated during T2 of the first INTA cycle and removed during T2 of the second INTA cycle.
QS1, QS0
24, 25
O
QUEUE STATUS: The queue status is valid during the CLK cycle after which the queue
operation is performed.
QS1 and QS2 provide status to allow external tracking of the internal HS-80C86RH instruction
queue. Note that QS1, QS0 never become high impedance.
QS1
QS0
0
0
No Operation
0
1
First Byte of Opcode from Queue
1
0
Empty the Queue
1
1
Subsequent Byte from Queue
The following pin function descriptions are for the HS-80C86RH in minimum mode (i.e. MN/MX = VDD). Only the pin functions which are
unique to minimum mode are described; all other pin functions are as described below.
M/IO
28
O
STATUS LINE: logically equivalent to S2 in the maximum mode. It is used to distinguish a mem-
ory access from an I/O access. M/IO becomes valid in the T4 preceding a bus cycle and remains
valid until the final T4 of the cycle (M = HIGH, IO = LOW). M/IO is held to a high impedance logic
zero during local bus “hold acknowledge”.
WR
29
O
WRITE: indicates that the processor is performing a write memory or write I/O cycle, depending
on the state of the M/IO signal. WR is active for T2, T3 and TW of any write cycle. It is active
LOW, and is held to high impedance logic one during local bus “hold acknowledge”.
INTA
24
O
INTERRUPT ACKNOWLEDGE: is used as a read strobe for interrupt acknowledge cycles. It is
active LOW during T2, T3 and TW of each interrupt acknowledge cycle. Note that INTA is never
floated.
ALE
25
O
ADDRESS LATCH ENABLE: is provided by the processor to latch the address into the 82C82
latch. It is a HIGH pulse active during clock LOW of Tl of any bus cycle. Note that ALE is never
floated.
DT/R
27
O
DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use a data bus
transceiver. It is used to control the direction of data flow through the transceiver. Logically, DT/R
is equivalent to S1 in maximum mode, and its timing is the same as for M/IO (T = HlGH, R =
LOW). DT/R is held to a high impedance logic one during local bus “hold acknowledge”.
DEN
26
O
DATA ENABLE: provided as an output enable fora bus transceiver in a minimum system which
uses the transceiver. DEN is active LOW during each memory and I/O access and for INTA
cycles. For a read or INTA cycle it is active from the middle of T2 until the middle of T4, while for
a write cycle it is active from the beginning of T2 until the middle of T4. DEN is held to a high
impedance logic one during local bus “hold acknowledge”.
HOLD
HLDA
31
I
HOLD: indicates that another master is requesting a local bus “hold”. To be a acknowledged,
30
O
HOLD must be active HIGH. The processor receiving the “hold” will issue a “hold acknowledge”
(HLDA) in the middle of a T4 or T1 clock cycle. Simultaneously with the issuance of HLDA, the
processor will float the local bus and control lines. After HOLD is detected as being LOW, the
processor will lower HLDA, and when the processor needs to run another cycle, it will again drive
the local bus and control lines.
HOLD is not an asynchronous input. External synchronization should be provided if the system
cannot otherwise guarantee the setup time.
Spec Number 518055
861
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