DS21Q41BTN Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS21Q41BTN

Quad T1 Framer

Dallas Semiconductor -> Maxim Integrated 

DS21Q41B

Receive Serial Data [RSER]. Received NRZ serial

data. Updated on rising edges of RCLK when the

receive side elastic store is disabled. Updated on the

rising edges of RSYSCLK when the receive side elastic

store is enabled.

Receive Sync [RSYNC]. An extracted pulse, one

RCLK wide, is output at this pin which identifies either

frame (RCR2.4=0) or multiframe boundaries

(RCR2.4=1). If set to output frame boundaries, then via

RCR2.5, RSYNC can also be set to output double–wide

pulses on signaling frames. If the receive side elastic

store is enabled, then this pin can be enabled to be an

input at which a frame boundary pulse is applied. See

Section 12 for timing details.

Receive Frame Sync (RFSYNC). An extracted 8 KHz

pulse, one RCLK wide, is output at this pin which identi-

fies frame boundaries. See Section 12 for timing

details.

Receive Multiframe Sync [RMSYNC]. Only used

when the receive side elastic store is enabled. An

extracted pulse, one RSYSCLK wide, is output at this

pin which identifies multiframe boundaries. If the

receive side elastic store is disabled, then this output

should be ignored. See Section 12 for timing details.

Receive Bipolar Data Inputs [RPOS and RNEG].

Sampled on falling edge of RCLK. Tie together to

receive NRZ data and disable bipolar violation monitor-

ing circuitry.

Receive System Clock [RSYSCLK]. 1.544 MHz or

2.048 MHz clock. Only used when the elastic store

function is enabled. Should be tied low in applications

that do not use the elastic store. Allowing this pin to float

can cause the device to 3–state it’s outputs.

Receive Loss of Sync/Loss of Transmit Clock

[RLOS/LOTC]. A dual function output. If CCR1.6=0,

then this pin will toggle high when the synchronizer is

searching for the T1 frame and multiframe. If

CCR1.6=1, then this pin will toggle high if the TCLK pin

has not been toggled for 5 µs.

Receive Alarm Interrupt [INT]. Flags host controller

during conditions defined in the Status Registers of the

four framers. User can poll the Interrupt Status Register

(ISR) to determine which status register in which framer

is active (if any). Active low, open drain output.

3–State Control [Test]. Set high to 3–state all output

and I/O pins (including the parallel control port). Set low

for normal operation. Useful in board level testing.

Bus Operation [MUX]. Set low to select non–multi-

plexed bus operation. Set high to select multiplexed bus

operation.

Data Bus [D0 to D7] or Address/Data Bus [AD0 to

AD7]. In non–multiplexed bus operation (MUX=0),

serves as the data bus. In multiplexed bus operation

(MUX=1), serves as a 8–bit multiplexed address/data

bus.

Address Bus [A0 to A5]. In non–multiplexed bus

operation (MUX=0), serves as the address bus. In mul-

tiplexed bus operation (MUX=1), these pins are not

used and should be tied low.

Bus Type Select [BTS]. Strap high to select Motorola

bus timing; strap low to select Intel bus timing. This pin

controls the function of the RD(DS), ALE(AS), and

WR(R/W) pins. If BTS=1, then these pins assume the

function listed in parenthesis ().

Read Input [RD] (Data Strobe [DS]).

Framer Selects [FS0 and FS1]. Selects which of the

four framers to be accessed.

Chip Selects [CS]. Must be low to read or write to any

of the four framers.

A6 or Address Latch Enable [ALE] (Address Strobe

[AS]). In non–multiplexed bus operation (MUX=0),

serves as the upper address bit. In multiplexed bus

operation (MUX=1), serves to demultiplex the bus on a

positive–going edge.

Write Input [WR] (Read/Write [R/W]).

Positive Supply [VDD]. 5.0 volts ±0.5volts.

Signal Ground [VSS]. 0.0 volts.

021997 9/55

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