DS21Q41BTN Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated
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DS21Q41BTN Datasheet PDF : 55 Pages
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DS21Q41B
DS21Q41B REGISTER MAP Table 1–5
ADDRESS R/W
REGISTER NAME
20
R/W Status Register 1
21
R/W Status Register 2
22
R/W Receive Information Register 1
23
R Line Code Violation Count
Register 1
24
R Line Code Violation Count
Register 2
25
R Path Code Violation Count
Register 1(1)
26
R Path Code Violation Count
Register 2
27
R Multiframe Out of Sync Count
Register 2
28
R Receive FDL Register
29
R/W Receive FDL Match Register 1
2A
R/W Receive FDL Match Register 2
2B
R/W Receive Control Register 1
2C
R/W Receive Control Register 2
2D
R/W Receive Mark Register 1
2E
R/W Receive Mark Register 2.
2F
R/W Receive Mark Register 3
30
R/W Common Control Register 3
31
R/W Receive Information Register 2
32
R/W Transmit Channel Blocking
Register 1
33
R/W Transmit Channel Blocking
Register 2
34
R/W Transmit Channel Blocking
Register 3
35
R/W Transmit Control Register 1
36
R/W Transmit Control Register 2
37
R/W Common Control Register 1
38
R/W Common Control Register 2
39
R/W Transmit Transparency Register 1
3A
R/W Transmit Transparency Register 2
3B
R/W Transmit Transparency Register 3
3C
R/W Transmit Idle Register 1
3D
R/W Transmit Idle Register 2
3E
R/W Transmit Idle Register 3
ADDRESS
3F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
REGISTER NAME
Transmit Idle Definition Register
Receive Signaling Register 1
Receive Signaling Register 2
Receive Signaling Register 3
Receive Signaling Register 4
Receive Signaling Register 5
Receive Signaling Register 6
Receive Signaling Register 7
Receive Signaling Register 8
Receive Signaling Register 9
Receive Signaling Register 10
Receive Signaling Register 11
Receive Signaling Register 12
Receive Channel Blocking
Register 1
Receive Channel Blocking
Register 2
Receive Channel Blocking
Register 3
Interrupt Mast Register 2
Transmit Signaling Register 1
Transmit Signaling Register 2
Transmit Signaling Register 3
Transmit Signaling Register 4
Transmit Signaling Register 5
Transmit Signaling Register 6
Transmit Signaling Register 7
Transmit Signaling Register 8
Transmit Signaling Register 9
Transmit Signaling Register 10
Transmit Signaling Register 11
Transmit Signaling Register 12
Test Register(2)
Test Register(2)
Transmit FDL Register
Interrupt Mask Register 1
NOTES:
1. Address 25 also contains Multiframe Out of Sync Count Register 1.
2. The Test Registers are used only by the factory; these registers must be cleared (set to all zeros) on pow-
er–up initialization to insure proper operation.
3. Any unused register address will allow the status of the interrupts to appear on the bus.
021997 10/55
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