CDP1854 Просмотр технического описания (PDF) - Intersil
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CDP1854 Datasheet PDF : 21 Pages
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CDP1854A, CDP1854AC
TPA
SCI
CPU
CDP1800
TPB
N0
EF3
T CLOCK R CLOCK
DAR
PI
SBS
RRD
WLS1
WLS2
EPE
THRL
UART
CDP1854A
TSRE
DMAI
BUS (8)
DA
T BUS
SDI
SDO
CLEAR
R BUS
MR
MODE
VSS
FIGURE 8. MODE 0 CONNECTION DIAGRAM
WORD LENGTH SELECT 2 (WLS2):
WORD LENGTH SELECT 1 (WLS1):
These two inputs select the character length (exclusive of
parity) as follows:
WLS2
Low
Low
High
High
WLS1
Low
High
Low
High
WORD LENGTH
5 Bits
6 Bits
7 Bits
8 Bits
EVEN PARITY ENABLE (EPE):
A high-level voltage at this input selects even parity to be
generated by the transmitter and checked by the receiver. A
low-level input selects odd parity.
TRANSMITTER CLOCK (TCLOCK):
Clock input with a frequency 16 times the desired transmitter
shift rate.
Description of Standard Mode 0 Operation
(Mode Input = VSS)
Initialization and Controls
The MASTER RESET (MR) input is pulsed, resetting the
Control, Status, and Receiver Holding Registers and setting
the SERlAL DATA OUTPUT (SDO) signal high. Timing is
generated from the clock inputs, Transmitter Clock
(TCLOCK) and Receiver Clock (RCLOCK), at a frequency
equal to 16 times the serial data bit rate. When the receiver
data input rate and the transmitter data output rate are the
same, the TCLOCK and RCLOCK inputs may be connected
together. The CONTROL REGISTER LOAD (CRL) input is
pulsed to store the control inputs PARITY INHIBIT (PI),
EVEN PARITY ENABLE (EPE), STOP BIT SELECT (SBS),
and WORD LENGTH SELECTs (WLS1 and WLS2). These
inputs may be hardwired to the proper voltage levels (VSS or
VDD) instead of being dynamically set and CRL may be
hardwired to VDD. The CDP1854A is then ready for
transmitter and/or receiver operation.
Transmitter Operation
For the transmitter timing diagram refer to Figure 10. At the
beginning of a typical transmitting sequence the Transmitter
Holding Register is empty (THRE is HIGH). A character is
transferred from the transmitter bus to the Transmitter Hold-
ing Register by applying a low pulse to the TRANSMITTER
HOLDING REGISTER LOAD (THRL) input causing THRE to
go low. If the Transmitter Shift Register is empty (TSRE is
HIGH) and the clock is low, on the next high-to-low transition
of the clock the character is loaded into the Transmitter Shift
Register preceded by a start bit. Serial data transmission
begins 1/2 clock period later with a start bit and 5-8 data bits
followed by the parity bit (if programmed) and stop bit(s). The
THRE output signal goes high 1/2 clock period later on the
high-to-low transition of the clock. When THRE goes high,
another character can be loaded into the Transmitter Holding
Register for transmission beginning with a start bit immedi-
ately following the last stop bit of the previous character. This
process is repeated until all characters have been transmit-
ted. When transmission is complete, THRE and Transmitter
Shift Register Empty (TSRE) will both be high. The format of
serial data is shown in Figure 12. Duration of each serial out-
put data bit is determined by the transmitter clock frequency
(fCLOCK) and will be 16/f CLOCK.
Receiver Operation
The receive operation begins when a start bit is detected at
the SERIAL DATA IN (SDl) input. After the detection of a
high-to-low transition on the SD line, a divide-by-16 counter
is enabled and a valid start bit is verified by checking for a
low-level input 7-1/2 receiver clock periods later. When a
valid start bit has been verified, the following data bits, parity
bit (if programmed), and stop bit(s) are shifted into the
Receiver Shift Register at clock pulse 7-1/2 in each bit time.
If programmed, the parity bit is checked, and receipt of a
valid stop bit is verified. On count 7-1/2 of the first stop bit,
the received data is loaded into the Receiver Holding Regis-
ter. If the word length is less than 8 bits, zeros (low output
voltage level) are loaded into the unused most significant
bits. If DATA AVAILABLE (DA) has not been reset by the time
the Receiver Holding Register is loaded, the OVERRUN
ERROR (OE) signal is raised. One-half clock period later,
the PARITY ERROR (PE) and FRAMlNG ERROR (FE) sig-
nals become valid for the character in the Receiver Holding
Register. The DA signal is also raised at this time. The three-
state output drivers for DA, OE, PE and FE are enabled
when STATUS FLAG DISCONNECT (SFD) is low. When
RECEIVER REGISTER DISCONNECT (RRD) goes low, the
receiver bus three-state output drivers are enabled and data
is available at the RECEIVER BUS (R BUS 0 - R BUS 7) out-
puts. Applying a negative pulse to the DATA AVAILABLE
RESET (DAR) resets DA. The preceding sequence of opera-
tion is repeated for each serial character received. A receiver
timing diagram is shown in Figure 11.
5-57
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