CDP1854 Просмотр технического описания (PDF) - Intersil

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CDP1854

Programmable Universal Asynchronous Receiver/Transmitter (UART)

Intersil 

CDP1854A, CDP1854AC

tCC

tCH

tCL

CLOCK 7 1/2

SAMPLE

CLOCK 7 1/2 LOAD

HOLDING REGISTER

R CLOCK

tDC

(NOTE 1)

SDI

1 2 3 4 5 6 7 16 1 2 3 4 5 6 7 8 9

START BIT

tTDA

PARITY

STOP BIT 1

tCDA

DA

READ

(NOTE 2)

tTT

TPB

OE

(NOTE 3)

PE

(NOTE 3)

FE

tCOE

tCPE

tCFE

NOTES:

1. If a start bit occurs at a time less than tDC before a high-to-low transition of the clock, the start bit may not be recognized until the next

high-to-low transition of the clock. The start bit may be completely asynchronous with the clock.

2. Read is the overlap of CS1, CS3, RD/WR = 1 and CS2 = 0. If a pending DA has not been cleared by a read of the Receiver Holding

Register by the time a new word is loaded into the Receiver Holding Register, the OE signal will come true.

3. OE and PE share terminal 15 and are also available as two separate bits in the status register.

FIGURE 4. MODE 1 RECEIVER TIMING DIAGRAM

TPB

(NOTE 1)

RSEL

T BUS 0-

T BUS 7

CS3, CS1

(NOTE 1)

tRSW

tDW

tTT

tWRS

tWD

RD/WR, CS2

(NOTE 1)

NOTE:

1. Write is the overlap of TPB, CS1, CS3 = 1 and CS2, RD/WR = 0.

FIGURE 5. MODE 1 CPU INTERFACE (WRITE) TIMING DIAGRAM

5-53

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