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74ALVT16260

12-bit to 24-bit multiplexed D-type latches (3-State)

Philips Electronics 

Philips Semiconductors

2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches

(3-State)

Product specification

74ALVT16260

FEATURES

• ESD protection exceeds 2000V per Mil-Std-883C, Method 3015;

exceeds 200V using machine model

• Latch-up protection exceeds 500mA per JEDEC Standard

JESD-17.

• Distributed VCC and GND pin configuration minimizes high-speed

switching noise.

• Output capability (–32mA IOH, 64mA IOL).

• Bus hold inputs eliminate the need for external pull-up resistors.

• 5V I/O compatible

• Live insertion/extraction permitted

• Power-up 3-State

• Power-up Reset

QUICK REFERENCE DATA

SYMBOL

PARAMETER

tPLH

tPHL

CIN

COUT

ICCZ

Propagation delay

nAx to nBx nBx to nAx

Input capacitance

Output capacitance

Total supply current

DESCRIPTION

The 74ALVT16260 is a 12-bit to 24-bit multiplexed D-type latch used

in applications where two separate data paths must be multiplexed

onto, or demultiplexed from, a single data path. Typical applications

include multiplexing and/or demultiplexing of address and data

information in microprocessor or bus-interface applications. This

device is alto useful in memory-interleaving applications.

Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are

available for address and/or data transfer. The output enable (OE1B,

OE2B, and OEA) inputs control the bus transceiver functions. The

OE1B and OE2B control signals also allow bank control in the A to

B direction.

Address and/or data information can be stored using the internal

storage latches. The latch enable (LE1B, LE2B, LEA1B, and

LEA2B) inputs are used to control data storage. When the latch

enable input is high, the latch is transparent. When the latch enable

input goes low, the data present at the inputs is latched and remains

latched until the latch enable input is returned high.

To ensure the high-impedance state during power-up or

power-down, OE should be tied to VCC through a pull-up resistor;

the minimum value of the resistor is determined by the current

sinking capability of the driver.

The 74ALVT16260 is available in a 56-pin Shrink Small Outline

Package (SSOP) and 56-pin Thin Shrink Small Outline Package

(TSSOP).

CONDITIONS

Tamb = 25°C; GND = 0V

CL = 50 pF

VI = 0 V or VCC

VI/O = 0 V or 5.0 V

Outputs disabled

TYPICAL

2.5V

3.3V

3.5

2.8

3.3

2.6

4

4

9

9

100

80

UNIT

ns

pF

pF

µA

ORDERING INFORMATION

PACKAGES

56-Pin Plastic SSOP Type III

56-Pin Plastic TSSOP Type II

TEMPERATURE RANGE

–40°C to +85°C

–40°C to +85°C

OUTSIDE NORTH AMERICA

74ALVT16260 DL

74ALVT16260 DGG

NORTH AMERICA

AV16260 DL

AV16260 DGG

DWG NUMBER

SOT371-1

SOT364-1

1998 Jan 30

2

853-2046-18918

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