82434LX Просмотр технического описания (PDF) - Intel

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82434LX

PCI, cache and memory controller (PCMC)

Intel 

82434LX 82434NX

Signal

BRDY

NA

AHOLD

EADS

INV

BOFF

HITM

Type

out

out

out

out

out

out

in

Description

BURST READY BRDY indicates that the system has responded in one of three ways

1 valid data has been placed on the Pentium processor data pins in response to a read

2 CPU write data has been accepted by the system or

3 the system has responded to a special cycle

NEXT ADDRESS The PCMC asserts NA for one clock when the memory system is

ready to accept a new address from the CPU even if all data transfers for the current

cycle have not completed The CPU may drive out a pending cycle two clocks after NA

is asserted and has the ability to support up to two outstanding bus cycles

ADDRESS HOLD The PCMC asserts AHOLD to force the Pentium processor to stop

driving the address bus so that either the PCMC or LBXs can drive the bus During PCI

master cycles AHOLD is asserted to allow the LBXs to drive a snoop address onto the

address bus If the PCI master locks main memory AHOLD remains asserted until the

PCI master locked sequence is complete and the PCI master negates PLOCK

AHOLD is asserted during all accesses to PCMC internal configuration registers to allow

configuration register accesses to occur over the A 31 0 lines

When in deturbo mode the PCMC periodically asserts AHOLD to prevent the processor

from initiating bus cycles in order to emulate a slower system The duration of AHOLD

assertion in deturbo mode is controlled by the Deturbo Frequency Control Register

(offset 51h) When PWROK is negated the PCMC asserts AHOLD to allow the strapping

options on A 31 28 to be read For more details on strapping options see the System

Clocking and Reset section

EXTERNAL ADDRESS STROBE The PCMC asserts EADS to indicate to the Pentium

processor that a valid snoop address has been driven onto the CPU address lines to

perform an inquire cycle During PCI master cycles the PCMC signals the LBXs to drive a

snoop address onto the host address lines and then asserts EADS to cause the CPU to

sample the snoop address

INVALIDATE The INV signal specifies the final state (invalid or shared) that a first level

cache line transitions to in the event of a cache line hit during a snoop cycle When

snooping the caches during a PCI master write the PCMC asserts INV with EADS

When INV is asserted with EADS an inquire hit results in the line being invalidated

When snooping the caches during a PCI master read the PCMC does not assert INV with

EADS In this case an inquire cycle hit results in a line transitioning to the shared state

BACKOFF The PCMC asserts BOFF to force the Pentium processor to abort all

outstanding bus cycles that have not been completed and float its bus in the next clock

The PCMC uses this signal to force the CPU to re-order a write-back due to a snoop cycle

around a currently outstanding bus cycle The PCMC also asserts BOFF to obtain the

CPU data bus for write-back cycles from the secondary cache due to a snoop hit The

CPU remains in bus hold until BOFF is negated

HIT MODIFIED The Pentium processor asserts HITM to inform the PCMC that the

current inquire cycle hit a modified line HITM is asserted by the Pentium processor two

clocks after the assertion of EADS if the inquire cycle hits a modified line in the primary

cache

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