82434LX Просмотр технического описания (PDF) - Intel

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82434LX

PCI, cache and memory controller (PCMC)

Intel 

82434LX 82434NX

 Low latency random access (60 ns write access

latency to slave registers from a master parked

on the bus)

 Capable of full concurrency with the processor

memory subsystem

 Full multi-master capability allowing any PCI mas-

ter peer-to-peer access to any PCI slave

 Hidden (overlapped) central arbitration

 Low pin count for cost effective component pack-

aging (multiplexed address data)

 Address and data parity

 Three physical address spaces memory I O

and configuration

 Comprehensive support for autoconfiguration

through a defined set of standard configuration

functions

Figure 2 Block Diagram of the 82430LX 82430NX PCIset EISA System

290479 – 3

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