V300PSC Просмотр технического описания (PDF) - QuickLogic Corporation

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V300PSC

PCI Bus Target Interface

QuickLogic Corporation 

V300PSC

Table 4: Signal Descriptions (cont’d)

Signal

LAD[31:0]

LA[5:2]

LD[31:0]

LA[31:2]

BE[3:0]

W/R

ALE

ADS

RDYRCV

READY

HOLD

HOLDA

LPAR[3:0]

BLAST

BTERM

LINT

LRST

LCLK

Type

I/O4

O4

I/O4

I/O4

I/O4

I/O4

I/O4

I/O4

I/O4

O4

I

I/O4

I/O4

I/O4

O4

I/O4

I

Local Bus Interface

R

Description

Z Local address and multiplexed data bus (multiplexed mode).

Z

Lower local address bus. Generated during local bus master

cycles and incremented during a burst (multiplexed mode).

Z Local data bus (de-multiplexed mode).

Z Local address bus (de-multiplexed mode).

Z Local bus byte enables.

Z Write/Read.

Z

Address Latch Enable: used to latch the address during the

address phase (multiplexed mode).

Z Asserted low to indicate the beginning of a bus cycle.

Z Local Bus data ready.

L

Local bus hold request: asserted by the P3PSC to initiate a local

bus master cycle.

Local bus hold acknowledge.

Z Local bus parity.

Z Burst last.

Z Bus Time-out. Burst terminate.

H Local interrupt request.

L/Z Local bus RESET signal.

Local bus clock.

Power and Ground Signals

Signal

Type R

Description

VCC

-

GND

-

POWER pins for connection to the board’s VCC plane.

GROUND pins for connection to the board’s GND plane.

a. R indicates state during reset.

4

V300PSC Data Sheet Rev 1.1

Copyright © 1997, V3 Semiconductor Corp.

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