V300PSC Просмотр технического описания (PDF) - QuickLogic Corporation
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V300PSC Datasheet PDF : 20 Pages
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V300PSC
Table 4: Signal Descriptions
Signal
AD[31:0]
C/BE[3:0]
PAR
FRAME
IRDY
TRDY
STOP
DEVSEL
IDSEL
PCLK
PRST
PERR
SERR
INT[A:D]
Type Ra
PCI Bus Interface
Description
PCI I/O Z Address and data, multiplexed on the same pins.
PCI I
Z Bus Command and Byte Enables, multiplexed on the same pins.
PCI I/O Z Parity represents even parity across AD[31:0] and C/BE[3:0].
PCI I
Z
Cycle Frame indicates the beginning and burst length of an
access.
PCI I
Z
Initiator Ready indicates the master agent is ready to complete
the current data phase of the transaction.
PCI O
Z
Target Ready indicates the target agent’s (V300PSC) ability to
complete the current data phase of the transaction.
PCI O
Z
Stop indicates the V300PSC is requesting the master to stop the
current transaction (retry or disconnect).
PCI O
Z
Device Select, indicates the V300PSC device has decoded its
address as the target of the current access.
PCI I
Initialization Device Select is used as a chip select during configu-
Z ration read and write transactions. It must be driven high in order
to access the chip’s internal configuration space.
PCI I
Z PCLK provides timing for all transactions on the PCI bus.
PCI I
Z Asserted low to bring all internal operations to a reset state.
PCI I/O
Z
Parity Error is used to report data parity errors during all PCI
transactions except a Special Cycle.
PCI I/OD
System Error is used to report address parity errors, data parity
Z errors on the Special Cycle command, or any other system error
where the result will be catastrophic.
PCI I/OD Z Level-sensitive interrupt requests may be received or generated.
Signal
SCL/LPERR
SDA
Type
O4
I/O4
Serial EEPROM Interface
R
Description
X EEPROM clock. Local parity error.
X EEPROM data.
Copyright © 1997, V3 Semiconductor Corp.
V300PSC Data Sheet Rev 1.1
3
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