CS4955-CQ Просмотр технического описания (PDF) - Cirrus Logic

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CS4955-CQ

NTSC/PAL Digital Video Encoder

Cirrus Logic 

CS4954 CS4955

DAC

Y

C

CVBS

R

G

B

Pin #

48

47

44

39

40

43

Mode 1

Y

C

CVBS_1

R

G

B

Mode 2

Y

C

CVBS_1

Cr (V)

Y

Cb (U)

Mode 3

Y

C

CVBS_1

-

CVBS_2

-

Mode 4

CVBS_2

-

CVBS_1

R

G

B

Mode 5

CVBS_2

-

CVBS_1

Cr (V)

Y

Cb (U)

Table 1. DAC configuration Modes

DACs has its own associated DAC enable bit. In

the Disable Mode, the 10-bit DACs source (or sink)

zero current.

When running the DACs with a low-impedance

load, a minimum of three DACs must be powered

down. When running the DACs with a high-imped-

ance load, all the DACs can be enabled simulta-

neously.

For lower power standby scenarios, the CS4954/5

also provides power shut-off control for the DACs.

Each DAC has an associated DAC shut-off bit.

4.8. Voltage Reference

The CS4954/5 is equipped with an on-board volt-

age reference generator (1.232 V) that is used by

the DACs. The internal reference voltage is accu-

rate enough to guarantee a maximum of 3% overall

gain error on the analog outputs. However, it is

possible to override the internal reference voltage

by applying an external voltage source to the VREF

pin.

4.9. Current Reference

The DAC output current-per-bit is derived in the

current reference block. The current step is speci-

fied by the size of resistor placed between the ISET

current reference pin and electrical ground.

A 4 kΩ resistor needs to be connected between

ISET pin and GNDA. The DAC output currents are

optimized to either drive a doubly terminated load

of 75 Ω (low impedence mode) or a double termi-

nated load of 300 Ω (high impedence mode). The 2

output current modes are software selectable

through a register bit.

4.10. Host Interface

The CS4954/5 provides a parallel 8-bit data inter-

face for overall configuration and control. The host

interface uses active-low read and write strobes,

along with an active-low address enable signal, to

provide microprocessor-compatible read and write

cycles. Indirect host addressing to the CS4954/5 in-

ternal registers is accomplished via an internal ad-

dress register that is uniquely accessible via bus

write cycles in which the host address enable signal

is asserted.

The CS4954/5 also provides an I2C-compatible se-

rial interface for device configuration and control.

This port can operate in standard (100Kb/sec) or

fast (400 Kb/sec) modes. When in I2C mode, the

parallel data interface pins, PDAT [7:0], can be

used as a general purpose I/O port controlled by the

I2C interface.

4.11. Closed Caption Services

The CS4954/5 supports the generation of NTSC

Closed Caption services. Line 21 and Line 284 cap-

tioning can be generated and enabled independent-

ly via a set of control registers. When enabled,

clock run-in, start bit, and data bytes are automati-

cally inserted at the appropriate video lines. A con-

venient interrupt protocol simplifies the software

interface between the host processor and the

CS4954/5.

DS278PP4

13

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