STLC1511 Просмотр технического описания (PDF) - STMicroelectronics

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STLC1511

NorthenLite™ G.lite BiCMOS Analog Front-End Circuit

STMicroelectronics 

Figure 2. The block diagram of the STLC1511

STLC1511

Bandgap/

Bias Gen

14-bit

DAC

fp=2M H z

TXON

TXOP

2

T X SIN [1:0]

FRMCLK

CK35M

2

RXSOUT [1:0]

D IG R E F

4.416M

14

35.328M/

17.622M

8/4

90

°

2/3 /4/8

5

2.56M

2.56M /35.328M

(Oscillator Mode)

FREF

35 .3 28 M

(External Clock M ode)

PFD

CP

VCAP

OSCNB

69

G

O S C P BREexstoenrantaolr

OSCPE

OSCNE

DIGCLK

ENB

DRX

DTX

4.416M

+

12 12-bit

ADC

-

-

+

G =1

+

-

fp= 2M H z

RX INN

-

+

RX OPINP

+

-

RXOPINN

RXINP

Shaded blocks are only usabe when the PLL is active. Crystal based external resonator for the CPE Mode, LC

based resonator for the CO Oscillator Mode. 35.328 MHz external reference in CO External Clock Mode.

3.2 Receive Path Specifications

Note: The first stage of the RxPGA provides a coarse gain of 0/20dB with a differential input or 6/26dB with a

single ended input. The second stage implements a programmable gain from 0dB to 20dB in 0.5dB steps.

5/31

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