MPC105 Overview
   The MPC105 provides a PowerPC reference platform-compliant bridge between PowerPC 601, PowerPC 603, and PowerPC 604 microprocessors and the PCI bus. PCI support allows system designers to rapidly design systems using peripherals already designed for PCI and the other standard interfaces available in the personal computer hardware environment. The MPC105 integrates secondary cache control and a high-performance memory controller that supports DRAM, synchronous DRAM (SDRAM), ROM, and Flash ROM. The MPC105 uses an advanced, 3.3 V CMOS process technology and is fully compatible with TTL devices.

MPC105 Features
Major features of the MPC105 are as follows:
• Processor interface
   — 60x processors supported at a wide range of frequencies
   — 32-bit address bus
   — Configurable 64- or 32-bit data bus
   — Accommodates an upgrade of either an external L2 cache or a secondary processor
   — Arbitration for secondary processor on-chip
   — Full memory coherency supported
   — Pipelining of 60x accesses
   — Store gathering on 60x-to-PCI writes
• Secondary (L2) cache control
   — Configurable for write-through or write-back operation
   — 256K, 512K, 1M sizes
   — Up to 4 Gbytes of cacheable space
   — Direct-mapped
   — Parity supported
   — Supports external byte decode or on-chip byte decode for write enables
   — Programmable timing supported
   — Synchronous burst and asynchronous SRAMs supported
• PCI interface
   — Compliant with PCI Local Bus Specification, Revision 2.0
   — Supports PCI interlocked accesses to memory using LOCK signal and protocol
   — Supports accesses to all PCI address spaces
   — Selectable big- or little-endian operation
   — Store gathering on PCI writes to memory
   — Selectable memory prefetching of PCI read accesses
   — Only one external load presented by the MPC105 to the PCI bus
   — PCI configuration registers
   — Interface operates at 16–33 MHz
   — Data buffering (in/out)
   — Parity supported
   — 3.3 V/5.0 V compatible
• Concurrent transactions on 60x and PCI buses supported
• Memory interface
   — Programmable timing supported
   — Supports either DRAM or SDRAM
   — High bandwidth (64-bit) data bus
   — Supports self-refreshing DRAM in sleep and suspend modes
   — Supports 1 to 8 banks built of x1, x4, x8, x9, x16, or x18 DRAMs
   — Supports PowerPC reference platform-compliant contiguous or discontiguous memory maps
   — 1 Gbyte of RAM space, 16 Mbytes of ROM space
   — Supports 8-bit asynchronous ROM or 32-/64-bit burst-mode ROM
   — Supports writing to Flash ROM
   — Configurable external buffer control logic
   — Parity supported
   — TTL compatible
• Power management
   — Fully-static 3.3 V CMOS design
   — Supports 60x nap, doze, and sleep power management modes, and suspend mode
• IEEE 1149.1-compliant, JTAG boundary-scan interface
• 304-pin ball grid array (BGA) package