Functional Description[1]
The CY7C1381D/CY7C1383D is a 3.3V, 512K x 36 and 1 Mbit x 18 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.

FEATUREs
• Supports 133-MHz bus operations
• 512K × 36/1M × 18 common I/O
• 3.3V –5% and +10% core power supply (VDD)
• 2.5V or 3.3V I/O supply (VDDQ)
• Fast clock-to-output time
   — 6.5 ns (133-MHz version)
   — 8.5 ns (100-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Offered in JEDEC-standard lead-free 100-pin TQFP ,119-ball BGA and 165-ball fBGA packages
• JTAG boundary scan for BGA and fBGA packages
• “ZZ” Sleep Mode option