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CS5394KS

117 dB, 48 kHz Audio A/D Converter

Cirrus Logic 

CS5394

full scale. Input signals can be AC or DC coupled.

The VCOM output is available to filter the internal

common mode and it is recommended that this out-

put be used to bias the analog input buffer to mini-

mize distortion. However, this pin is not intended

to supply significant amounts of current and is sus-

ceptable to noise coupling into the sampling cir-

cuits. Please refer to the CDB5394 for a suggested

implementation.

+3.5 V

+2.5 V

+1.5 V

+3.5 V

+2.5 V

+1.5 V

CS5394

AIN+

AIN-

Full Scale Input level= (AIN+) - (AIN-)= 4.0 Vpp

Figure 4. Full Scale Input Voltage

The CS5394 samples the analog inputs at 64× Fs,

3.072 MHz for a 48 kHz sample-rate. The digital

filter rejects all noise above 26.6 kHz except for

frequencies at 3.072 MHz ±22.1 kHz (and multi-

ples of 3.072 MHz). Most audio signals do not have

significant energy at 3.072 MHz. Nevertheless, a

39 Ω resistor in series with each analog input and a

3.9 nF capacitor across the inputs will attenuate any

noise energy at 3.072 MHz, in addition to provid-

ing the optimum source impedance for the modula-

tors. The use of capacitors which have a large

voltage coefficient must be avoided since these will

degrade signal linearity. NPO and COG capacitors

are recommended. If active circuitry precedes the

ADC, it is recommended that the above RC filter is

placed between the active circuitry and the AINR

and AINL pins. The above example frequencies

scale linearly with sample rate.

The on-chip voltage reference is available at VREF

for the purpose of decoupling only. The circuit

traces attached to this pin must be minimal in

length and no load current may be taken from

VREF. The recommended decoupling scheme,

Figure 1, is a 100 µF electrolytic capacitor and a

0.1 µF ceramic capacitor connected from VREF to

AGND. The decoupling capacitors, particularly the

0.1 µF, must be positioned to minimize the electri-

cal path from VREF and pin 3, AGND, on the

printed circuit board.

High Pass Filter

The CS5394 includes a high pass filter after the

decimator to remove the indeterminate DC offsets

introduced by the analog buffer stage and the

CS5394 analog modulator. The first-order high

pass filter are detailed in the Digital Filter specifi-

cations table. The filter response scales linearly

with sample rate.

Power-up and Calibration

Reliable power-up can be accomplished by with-

holding the MCLKA/D until the 5 Volt power and

configuration pins are stable. It is also recommend-

ed that the MCLKA/D be removed if the supplies

drop below 4.75 Volt to prevent power glitch relat-

ed issues.

The delta-sigma modulators settle in a matter of

microseconds after the analog section is powered,

either through the application of power or by exit-

ing the power-down mode. However, the voltage

reference will take much longer to reach a final val-

ue due to the presence of external capacitance on

the VREF pin.

A calibration of the tri-level delta-sigma modulator

should always be initiated following power-up and

after allowing sufficient time for the voltage on the

external VREF capacitor to settle. This is required

to minimize noise and distortion. Calibration is ac-

tivated on a rising edge applied to the CAL pin and

requires 4100 LRCK cycles. It is also advised that

the CS5394 be calibrated after the device has

reached thermal equilibrium to maximize perfor-

mance.

DS258PP4

11

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