ML2008, ML2009
D8
D7 D6 D5 D4 D3 D2 D1 BIT
A0 = 0 ATTEN/GAIN C3 C2 C1 C0 F3 F2 F1 REG 0
A0 = 1
PDN F0 REG 1
Figure 10. ML2008 Register Structure
D8
D7 D6 D5 D4 D3 D2 D1 D0 BIT
ATTEN/GAIN C3 C2 C1 C0 F3 F2 F1 F0 REG 0
Figure 11. ML2009 Register Structure
ML2008
VIN
VOUT
CS WR A0 D1-D8
µP
8
Figure 12. Typical 8-Bit µP Interface, Double Write
ML2009
VIN
VOUT
CS WR D1-D8 D0
+5V
µP
8
Figure 13. Typical 8-Bit µP Interface, Single Write
ML2009
CS WR D0-D8
µP
9
Figure 14. Typical 16-Bit µP Interface
8
ML2009
VIN
VOUT
D0-D8 WR CS
ML2233
VIN
12-BIT
+ SIGN
A/D
µP
OR
DSP
Figure 15. AGC for DSP or Modem Front End