Figure 22-1: CPC Signal...................................................................................................................................................... 22-1
Figure 22-2. CPC Operation Flowchart ............................................................................................................................... 22-2
Figure 22-3: CPC Operation (with CPCThreshold = 4)........................................................................................................ 22-3
Figure 22-4: CPC Block Diagram ........................................................................................................................................ 22-4
Figure 23-1. System Configuration One .............................................................................................................................. 23-1
Figure 23-2. System Configuration Two .............................................................................................................................. 23-2
Figure 23-3. System Configuration Three............................................................................................................................ 23-2
Figure 24-1. The ARM Bus System Block Diagram............................................................................................................. 24-2
Figure 24-2. SDRAM Setup and Hold Timing .................................................................................................................... 24-29
Figure 24-3. SDRAM Read or Write Timing....................................................................................................................... 24-30
Figure 24-4. SDRAM Mode Timing.................................................................................................................................... 24-30
Figure 24-5. SDRAM Refresh Timing ................................................................................................................................ 24-30
Figure 24-6. FPDRAM Timing (Read or Write) .................................................................................................................. 24-31
Figure 24-7. FPDRAM Timing (Refresh)............................................................................................................................ 24-33
100723A
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