MFC2000 Просмотр технического описания (PDF) - Conexant Systems

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MFC2000

Multifunctional Peripheral Controller 2000

Conexant Systems 

Multifunctional Peripheral Controller 2000

3. Hardware Interface

MFC2000

3.1 Pin Description

Pin Name

PRTIRQn

AUXCLK

A[11:0]/A[23:12]

ALE

AE[2]/GPO[14]/SSTXD2/

ROM_CONFIG[0]

AO[2]/GPO[15]/SSSTAT2/RO

M_CONFIG[1]

AE[3]/GPO[16]/

CLK_CONFIG[0]

AO[3]/GPO[17]/

CLK_CONFIG[1]

D[15:0]

RDn

WREn/DOEEn

WROn/DOEOn

ROMCSn

CS[1]n

CS[0]n

RASn[1:0]

CASOn[1:0]

Table 3-1. Pin Description (1 of 6)

Pin No.

I/O

U14

I

K20

O

A20,B20,B19,B I/O

18,B17,C20,C1

9,C18,C17,D20,

D19,D18

C16

O

A19

I/O

A18

I/O

A17

I/O

D16

I/O

A12,B12,C12,A I/O

13,B13,C13,D1

3,A14,B14,C14,

A15,B15,C15,D

15,A16,B16

D12

O

B9

O

C9

O

D10

O

A9

O

G18

O

F19,F18

O

E17,F20

O

Input

Type

HU5VT

-

5VT

-

D5VT

D5VT

D5VT

D5VT

5VT

-

-

-

-

-

3V

-

-

Output

Type

-

2XT3V

3XT5VT

Pin Description

(Hysteresis, Pull up) Interrupt from the external

printing ASIC (active low)

Auxiliary clock output for using as the master clock

for external devices

Address bus (12-bit), A[23:12] and A[11:0] are

muxed out through same pins.

2XT5VT

2XT5VT

2XT5VT

2XT5VT

2XT5VT

2XT5VT

Address Latch output signal for latching A[23:12]

externally

(Pull down) Address bit for external ROM mux in

the ROM interleave access mode or GPO[14] or

TX data output for SSIF2 (ROM_CONFIG[0] input

during the reset period)

(Pull down) Address bit for external ROM mux in

the ROM interleave access mode or GPO[15] or

Status input for SSIF2 (ROM_CONFIG[1] input

during the reset period)

(Pull down) Address bit for external ROM mux in

the ROM interleave access mode or GPO[16]

(CLK_CONFIG[0] input during the reset period)

(Pull down) Address bit for external ROM mux in

the ROM interleave access mode or GPO[17]

(CLK_CONFIG[1] input during the reset period)

Data bus (16-bit)

3XT5VT

4XT5VT

4XT5VT

2XT5VT

2XT5VT

2XT3V

2XT3V

2XT3V

Read strobe (active low)

Write strobe for the lower byte (active low) or

DRAM output enables selects used for non-

interleave mode and interleave modes. DOEEn is

used for reading the even address bank (active

low).

Write strobe for the higher byte (active low) or

DRAM output enables selects used for non-

interleave mode and interleave modes. DOEOn is

used for reading the odd address bank (active

low).

ROM chip select (active low)

I/O chip select (active low).

SRAM chip select (active low) (VRTC powered)

DRAM row Address select for bank 0 and 1(active

low) (VDRAM powered)

DRAM column odd address selects used for non-

interleave mode and interleave mode. (VDRAM

powered)

100723A

Conexant

3-1

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