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T8532-JL-TR

Multichannel Programmable Codec Chip Set

Agere -> LSI Corporation 

Preliminary Data Sheet

November 2000

T8531/T8532 Multichannel Programmable

Codec Chip Set

Table of Contents (continued)

Tables

Page

Table 1. T8532 Pin Descriptions ................................. 8

Table 2. T8531 Pin Descriptions ............................... 10

Table 3. Active Time-Slot Spacing in a PCM

Bus Frame ................................................... 15

Table 4. DSP Engine RAM Map for Channel_0 ac

Path Coefficients ......................................... 17

Table 5A. Bit Map for DSP Engine Time-Slot

Control Word............................................. 18

Table 5B. Bit Map for Default Per-Board

Coefficient Tables...................................... 18

Table 6. DSP Engine RAM Map for Time-Slot

Information Table 0...................................... 18

Table 7. Summary of Microprocessor Commands

for Control of T8531 Data Processing ......... 20

Table 8. Digital Interface............................................ 24

Table 9. Analog Interface .......................................... 24

Table 10. T8532 Power Dissipation...........................25

Table 11. T8531 Power Dissipation...........................25

Table 12. Gain and Dynamic Range ......................... 25

Table 13. Noise (per Channel) ..................................27

Table 14. Distortion and Group Delay ....................... 28

Table 15. Crosstalk.................................................... 28

Table 16. PCM Interface Timing ............................... 29

Table 17. Serial Control Port Timing ........................ 31

Table 18. DSP Engine RAM Memory Map ................ 32

Table 19. T8531 Time-Slot Assignment Memory

Map ...........................................................34

Table 20A. Bit Map for T8531 Time-Slot Assignment

Registers at 0x1400—0x140F................. 34

Table 20B. Bit Map for CTZ Disable and Null

Channel................................................... 34

Table 21. T8531 Channel Register Memory Map

for T8532 Device 0 ................................... 35

Table 22. T8531 Channel Register Memory Map

for T8532 Device 1 ................................... 35

Table 23. Bit Map for T8532 Powerup/Powerdown

Registers at 0x1500—0x1507 and

0x1540—0x1547 ....................................... 35

Table 24. Bit Map for T8532 Channel Control

Register 1 at 0x1508—0x150F and

0x1548—0x154F .......................................36

Table 25. T8532 Control Register 1: Transmit

Gain ...........................................................36

Table 26. T8532 Control Register 1: Analog

Termination Impedance.............................36

Table 27. T8532 Control Register 1: Digital

Loopback ...................................................37

Table 28. Bit Map for T8532 All Channel Test

Register at 0x1510 and 0x1550.................37

Table 29. Bits 3:0 of T8532 All Channel Test

Register at 0x1510 and 0x1550.................37

Table 30. Bit Map for T8532 Channel Control

Register 2 at 0x1518—0x151F and

0x1558—0x155F .......................................38

Table 31. T8532 Control Register 2: Receive Gain ...38

Table 32. T8531 Control Register Map .....................38

Table 33. Bits 15:8 of T8531 Board Control Word 1

at 0x1FFE ..................................................39

Table 34. Bits 7:0 of T8531 Board Control Word 1

at 0x1FFE ..................................................39

Table 35. Bits 15:9 of T8531 Board Control Word 2

at 0x1FFC..................................................40

Table 36. Bits 8:0 of T8531 Board Control Word 2

at 0x1FFC..................................................40

Table 37. Bits 15:0 of T8531 Board Control Word 3

at 0x1FFA ..................................................40

Table 38. Bits 15:0 of T8531 Board Control Word 4

at 0x1FF8 ..................................................40

Table 39. Bits 15:0 of T8531 Board Control Word 5

at 0x1FF6 ..................................................40

Table 40. Bits 15:0 of T8531 Reset of

Microprocessor Commands at 0x7FFF .....40

Table 41. DSP Engine ROM Memory Map................41

Table 42. Transmit Path Group Delay vs. Bit Offset ..48

Lucent Technologies Inc.

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