CS493005-CL Просмотр технического описания (PDF) - Cirrus Logic

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CS493005-CL

Multi-Standard Audio Decoder Family

Cirrus Logic 

CS49300 Family DSP

1.14. Switching Characteristics — Parallel Data Input

(VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)

Parameter

Symbol

Min

CMPCLK Period

Tcmpclk

4*DCLK + 10

DATA[7:0] setup before CMPCLK high

Tcmpsu

10

DATA[7:0] hold after CMPCLK high

Tcmphld

10

Delay from falling edge of CMPREQ to CMPCLK rising edge Treqclk

0

Max

Unit

-

ns

-

ns

-

ns

-

ns

Notes: 1. CMPREQ signal is asynchronous to CLKIN and can change at any time relative to CLKIN.

2. Certain timing parameters are normalized to the DSP clock, DCLK, in nanoseconds. The DSP clock can

be defined as follows:

External CLKIN Mode:

DCLK == CLKIN/4 before and during boot

DCLK == CLKIN after boot

Internal Clock Mode:

DCLK == 10MHz before and during boot, i.e. DCLK == 100ns

DCLK == 65 MHz after boot, i.e. DCLK == 15.4ns

It should be noted that DCLK for the internal clock mode is application specific. The application code

users guide should be checked to confirm DCLK for the particular application.

CMPREQ

Treqclk

CMPCLK

DATA[7:0]

Tcmpsu

Tcmpclk

Tcmphld

Figure 11. Parallel Data Timing (when not in a parallel control mode)

DS339F7

21

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