CS493112-CL Просмотр технического описания (PDF) - Cirrus Logic

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CS493112-CL

Multi-Standard Audio Decoder Family

Cirrus Logic 

CS49300 Family DSP

1.10. Switching Characteristics — SPI™ Control Port

(VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)

Parameter

Symbol

SCCLK clock frequency

(Note 1) fsck

CS falling to SCCLK rising

tcss

Rise time of SCCLK line

(Note 7)

tr

Fall time of SCCLK lines

(Note 7)

tf

SCCLK low time

tscl

SCCLK high time

tsch

Setup time SCDIN to SCCLK rising

tcdisu

Hold time SCCLK rising to SCDIN

(Note 2) tcdih

Transition time from SCCLK to SCDOUT valid

(Note 3) tscdov

Time from SCCLK rising to INTREQ rising

(Note 4) tscrh

Rise time for INTREQ

(Note 4)

trr

Hold time for INTREQ from SCCLK rising

(Note 5, 7) tscrl

Time from SCCLK falling to CS rising

tsccsh

High time between active CS

tcsht

Time from CS rising to SCDOUT high-Z

(Note 7) tcscdo

Min

Max Units

-

2000

kHz

20

-

ns

-

50

ns

-

50

ns

150

-

ns

150

-

ns

50

-

ns

50

-

ns

-

40

ns

-

200

ns

- (Note 6) ns

0

-

ns

20

-

ns

200

-

ns

20

ns

Notes: 1. The specification fsck indicates the maximum speed of the hardware. The system designer should be

aware that the actual maximum speed of the communication port may be limited by the software. The

relevant application code user’s manual should be consulted for the software speed limitations.

2. Data must be held for sufficient time to bridge the 50 ns transition time of SCCLK.

3. SCDOUT should not be sampled during this time period.

4. INTREQ goes high only if there is no data to be read from the DSP at the rising edge of SCCLK for the

second-to-last bit of the last byte of data during a read operation as shown.

5. If INTREQ goes high as indicated in (Note 4), then INTREQ is guaranteed to remain high until the next

rising edge of SCCLK. If there is more data to be read at this time, INTREQ goes active low again. Treat

this condition as a new read transaction. Raise chip select to end the current read transaction and then

drop it, followed by the 7-bit address and the R/W bit (set to 1 for a read) to start a new read transaction.

6. With a 3.3k Ohm pull-up resistor this value is typically 260ns. As this pin is open drain adjusting the pull

up value will affect the rise time.

7. This time is by design and not tested.

14

DS339F7

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