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W78C/E354 Просмотр технического описания (PDF) - Winbond

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W78C/E354
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W78C/E354 Datasheet PDF : 44 Pages
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W78C354
On-Chip
Program Memory
3FFFH
On-Chip
Data Memory
0000H
Figure 1-1
FFH
(MOVX @Ri)
00H
Figure 1-2
FFH
SFR
Scratchpad
RAM
80H (Direct Addressing)
7FH Scratchpad
RAM
(Direct/Indirect
00H Addressing)
(Indirect Addressing)
Figure 1-3
Figure 1. Memory address space
B. Modified 80C32 SFRs
1. Timer/Counter Control Register (TCON):
BIT
NAME
FUNCTION
TCON.7
TCON.6
TCON.5
TCON.4
TCON.3
TCON.2
TF1 Timer 1 overflow flag.
Set by hardware on timer/counter overflow. Cleared by hardware when
processor vectors to interrupt routine.
TR1 Timer 1 run control bit.
Set/cleared by software to turn timer/counter on or off.
TF0 Timer 0 overflow flag.
Set by hardware on timer/counter overflow. Cleared by hardware when
processor vectors to interrupt routine.
TR0 Timer 0 run control bit.
Set/cleared by software to turn timer/counter on or off.
-
Reserved
-
Reserved
TCON.1
TCON.0
IE0 Interrupt 0 edge flag.
Set by hardware when external interrupt edge detected. Cleared by
hardware when interrupt processed.
IT0 Interrupt 0 type control bit.
Set/cleared by software to specify falling edge/low level triggered external
interrupt.
Note: The registers in the shaded region are modified from the 80C32 SFRs.
-8-

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