AD679AJ Просмотр технического описания (PDF) - Analog Devices
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AD679AJ Datasheet PDF : 12 Pages
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AD679
CONVERSION CONTROL
In synchronous mode (SYNC = HIGH), both Chip Select (CS)
and Start Convert (SC) must be brought LOW to start a con-
version. CS should be LOW tSC before SC is brought LOW. In
asynchronous mode (SYNC = LOW), a conversion is started by
bringing SC low, regardless of the state of CS.
Before a conversion is started, End-of-Convert (EOC) is HIGH
and the sample-hold is in track mode. After a conversion is
started, the sample-hold goes into hold mode and EOC goes
LOW, signifying that a conversion is in progress. During the
conversion, the sample-hold will go back into track mode and
start acquiring the next sample.
In track mode, the sample-hold will settle to ± 0.003% (14 bits)
in 1.5 µs maximum. The acquisition time does not affect the
throughput rate as the AD679 goes back into track mode more
than 2 µs before the next conversion. In multichannel systems,
the input channel can be switched as soon as EOC goes LOW.
Bringing OE LOW tOE after CS goes LOW makes the output
register contents available on the output data bits (DB7–DB0).
A period of time tCD is required after OE is brought HIGH be-
fore the next SC instruction is issued.
If SC is held LOW, conversion accuracy may deteriorate. For
this reason, SC should not be held low in an attempt to operate
in a continuously converting mode.
START CONVERSION TRUTH TABLE
INPUTS
SYNC CS SC STATUS
1
1 X No Conversion
Synchronous
1
0 f Start Conversion
Mode
1
f 0 Start Conversion
(Not Recommended)
1
0 0 Continuous Conversion
(Not Recommended)
0
Asynchronous 0
Mode
0
X 1 No Conversion
X f Start Conversion
X 0 Continuous Conversion
(Not Recommended)
NOTES
1 = HIGH voltage level.
0 = LOW voltage level.
X = Don’t care.
= HIGH to LOW transition. Must stay low for t = tCP.
14-BIT MODE CODING FORMAT (1 LSB = 0.61 mV)
Unipolar Coding
(Straight Binary)
Bipolar Coding
(Twos Complement)
VIN*
0.00000 V
5.00000 V
9.99939 V
Output Code
000 . . . 0
100 . . . 0
111 . . . 1
VIN*
–5.00000 V
–0.00061 V
0.00000 V
+2.50000 V
+4.99939 V
Output Code
100 . . . 0
111 . . . 1
000 . . . 0
010 . . . 0
011 . . . 1
*Code center.
END-OF-CONVERT
In asynchronous mode, End-of-Convert (EOC) is an open drain
output (requiring a minimum 3 kΩ pull-up resistor) enabled by
End-of-Convert Enable (EOCEN). In synchronous mode, EOC
is a three-state output which is enabled by EOCEN and CS. See
Conversion Status Truth Table. Access (tBA) and float (tFD)
timing specifications do not apply in asynchronous mode where
they are a function of the time constant formed by the external
load capacitance and the pull-up resistor.
OUTPUT ENABLE OPERATION
The data bits (DB7–DB0) are three-state outputs that are en-
abled by Chip Select (CS) and Output Enable (OE). CS should
be LOW tOE before OE is brought LOW.
When EOC goes HIGH, the conversion is completed and the
output data may be read. The output is read in two steps as a
16-bit word, with the high byte read first, followed by the low
byte. High Byte Enable (HBE) controls the output sequence.
The 14-bit result is left justified within the 16-bit field.
In unipolar mode (BIPOFF tied to AGND), the output coding
is straight binary. In bipolar mode (BIPOFF tied to REFOUT),
output coding is twos-complement binary.
POWER-UP
The AD679 typically requires 10 µs after power-up to reset in-
ternal logic.
CONVERSION STATUS TRUTH TABLE
INPUTS
OUTPUT
SYNC CS EOCEN EOC
STATUS
10
10
Synchronous 1 1
Mode
1X
00
Converting
01
Not Converting
X High Z Either
1 High Z Either
0X
Asynchronous 0 X
Mode*
0X
00
Converting
0 High Z Not Converting
1 High Z Either
NOTES
1 = HIGH voltage level.
0 = LOW voltage level.
X = Don’t care.
*EOC requires a pull-up resistor in asynchronous mode.
OUTPUT ENABLE TRUTH TABLE
INPUTS
HBE (CS U OE)
X
1
OUTPUTS
DB7 . . . DB0
← High Z →
Unipolar or
0
0
Bipolar
1
0
abcdefgh
i j k l mn00
NOTES
1 = HIGH voltage level. a = MSB.
0 = LOW voltage level. n = LSB.
X = Don’t care.
U = Logical OR.
Data coding is binary for Unipolar Mode and 2s Complement Binary for Bipolar
Mode.
–8–
REV. C
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