74ALVCH16600DGG Просмотр технического описания (PDF) - Nexperia B.V. All rights reserved
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74ALVCH16600DGG Datasheet PDF : 17 Pages
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Nexperia
74ALVCH16600
18-bit universal bus transceiver; 3-state
5.2 Pin description
Table 2. Pin description
Symbol
A0, A1, A2, A3, A4, A5, A6, A7, A8,
A9, A10, A11, A12, A13, A14, A15, A16, A17
B0, B1, B2, B3, B4, B5, B6, B7, B8,
B9, B10, B11, B12, B13, B14, B15, B16, B17
OEAB, OEBA
Pin
3, 5, 6, 8, 9, 10, 12, 13, 14,
15, 16, 17, 19, 20, 21, 23, 24, 26
54, 52, 51, 49, 48, 47, 45, 44, 43,
42, 41, 40, 38, 37, 36, 34, 33, 31
1, 27
LEAB, LEBA
2, 28
CPBA, CPAB
30, 55
CEBA, CEAB
29, 56
GND
VCC
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
Description
data inputs/outputs
data outputs/inputs
A to B / B to A output enable input
(active LOW)
A to B / B to A latch enable inputs
(active HIGH)
B to A / A to B clock inputs
(active LOW)
B to A / A to B clock enable inputs
(active LOW)
ground (0 V)
supply voltage
6 Functional description
Table 3. Function selection [1] [2]
Operating mode
Inputs
CEAB
OEAB
LEAB
CPAB
An
Disabled
X
H
X
X
X
Transparent
X
L
H
X
H
X
L
H
X
L
Hold
H
L
L
X
X
Clock data & Display
L
L
L
↓
h
L
L
L
↓
l
Hold data & Display
L
L
L
H
X
L
L
L
L
X
[1] A-to-B data flow is shown; B-to-A flow is similar but uses CEBA, OEBA, LEBA, and CPBA.
[2] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the enable or clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the enable or clock transition;
X = don’t care;
NC = no change
↓ = HIGH-to-LOW enable or clock transition;
Z = high-impedance OFF-state.
Outputs
Bn
Z
H
L
NC
H
L
NC
NC
74ALVCH16600
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 15 January 2018
© Nexperia B.V. 2018. All rights reserved.
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