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UPD78C11AGF(A)-XXX-3BE Просмотр технического описания (PDF) - NEC => Renesas Technology

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UPD78C11AGF(A)-XXX-3BE
NEC
NEC => Renesas Technology NEC
UPD78C11AGF(A)-XXX-3BE Datasheet PDF : 60 Pages
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µPD78C10A(A), 78C11A(A), 78C12A(A)
1. PIN FUNCTIONS
1.1 Pin Function List
Pin name
I/O
Function
PA7-0
I/O
Port A is an 8-bit I/O port for which the input or output mode can be specified bit-wise.
(Port A)
PB7-0
I/O
Port B is an 8-bit I/O port for which the input or output mode can be specified bit-wise.
(Port B)
PC0/TxD
I/O or O
Port C
Transmit Data
When used as port C, it is an 8-bit I/O port for When used for transmit data output, it is a
which the input or output mode can be speci- serial data output pin.
PC1/RxD
I/O or I fied bit-wise.
Receive Data
When used for receive data input, it is a
serial data input pin.
PC2/SCK
I/O or I/O
Serial Clock
When used for serial clock I/O, it is an
output pin for the internal clock or an input
pin for an external clock.
PC3/INT2/TI I/O or I or I
Interrupt Request/Timer Input
When used for interrupt request or timer
input, it is a falling-edge triggered maskable
interrupt input pin, or a timer input pin for
external clock input, or an AC-input, zero-
cross detection pin.
PC4/TO
I/O or O
Timer Output
When used for timer output, it outputs a
square wave having a count time of one-
half cycle per internal clock cycle.
PC5/CI
I/O or I
Counter Input
When used for counter input, it is an input
pin for external pulses to the timer/event
counter.
PC6/CO0
I/O or O
Counter Output0, 1
PC7/CO1
When used for counter outputs 0 and 1,
these pins output a programmable square
wave from the timer/event counter.
PD7-0/AD7-0
I/O or I/O Port D
Address/Data Bus
When used as Port D, it is an 8-bit I/O port for When using external memory, it acts as a
which the input or output mode can be speci- multiplexed address/data bus.
fied byte-wise (µPD78C11A(A)).
PF7-0/AB15-8
I/O or O
Port F
Address Bus
When used as Port F, it is an 8-bit I/O port for When using external memory, it acts as an
which the input or output mode can be speci- address bus.
fied bit-wise.
WR
O
This is a strobe signal that is output for external memory write operations. It goes high
(Write Strobe)
except during the external memory’s data write cycle. Output has high impedance when
the RESET signal is low or during hardware STOP mode.
RD
O
This is a strobe signal that is output for external memory read operations. It goes high
(Read Strobe)
except during the external memory’s data read cycle. Output has high impedance when
the RESET signal is low or during hardware STOP mode.
ALE
O
A strobe signal is used to externally latch the low-order address data output to PD0 to
(Address Latch
PD7 for external memory access. Output has high impedance when the RESET signal
Enable)
is low or during hardware STOP mode.
8

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