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WT21-A-HCI Datasheet PDF : 57 Pages
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9
Power Control and Regulation
9.1
Power Control and Regulation
WT21 contains two linear regulators.
A high voltage regulator to generate 1,8 V rail for the module I/Os
A low voltage regulator to supply the 1,5 V core from the 1,8 V rail
The module can be powered from a high-voltage rail through both regulators and the output of
the high-voltage regulator can be used as a supply voltage for the digital interfaces of the
module (VDD_PADS). Alternatively VDD_PADS can be supplied by an external voltage source
and 1V8 regulator can be by-passed by connecting 1.8 V from an external regulator directly to
1V8_OUT. if the I/O supply VDD_PADS is powered before the 1.5V supplies the digital pads
default to their No Core Voltage Reset state.
VREGIN
1V8_OUT
VREG_ENA
1V8 linear
regulator
1V5 linear
regulator
RF
circuitry
VDD_PADS
Digital circuitry and interfaces
Figure 28: Voltage Regulator Configuration
9.2
VREG_ENABLE
The regulator enable pin VREGENABLE is used to enable the WT21. VREGENABLE enables both
the high voltage regulator and the low voltage regulator.
The pin is active high, with a logic threshold of around 1V, and has a weak pull-down.
VREGENABLE can tolerate voltages up to 4.9V, so may be connected directly to a battery to
enable the device.
9.3
RST#
WT21 may be reset from several sources: RST# pin, power on reset, a UART break character or
via a software configured watchdog timer.
The RST# pin is an active low reset and is internally filtered using the internal low frequency
clock oscillator. A reset is performed between 1.5 and 4.0ms following RST# being active. It is
recommended that RST# be applied for a period greater than 5ms.
The power on reset occurs when the core supply falls below typically 1.24V and is released
when core voltage rises above typically 1.31V. At reset the digital I/O pins are set to inputs for
bi-directional pins and outputs are tri-state. The pull-down state is shown in Table 21. Following
a reset, WT21 assumes the maximum XTAL frequency, which ensures that the internal clocks
run at a safe (low) frequency until WT21 is configured for the actual XTAL frequency.
Bluegiga Technologies Oy
Page 41 of 56
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