WED9LAPC2C16V4BC Просмотр технического описания (PDF) - White Electronic Designs => Micro Semi

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WED9LAPC2C16V4BC

512K x 32 SSRAM / 512K x 64 SDRAM

White Electronic Designs => Micro Semi 

WED9LAPC2C16V4BC

FIG. 1 PIN CONFIGURATION (CONTINUED)

PIN DESCRIPTION

Symbol

CADDR

CDATA

CWE

COE

VCADDR

VCDATA

VCBS

VCDQM

VCRAS

VCCAS

VCWE

GCLK

VCC

VSS

Pin Name

CRAM Address

CRAM Data

CRAM write enable

CRAM output enable

VCRAM address

VCRAM data

VCRAM bank select

VCRAM DQM

VCRAM row address strobe

VCRAM column address strobe

VCRAM write enable

Global clock

Power supply

Ground

Description

Address pins for the SSRAM that serves as the control RAM (CRAM)

Data I/O pins for the SSRAM control memory (CRAM)

Write enable control for the SSRAM control memory (CRAM)

Output enable control pin for the SSRAM control memory (CRAM)

Address pins for the SDRAM memory that serves as the virtual connection memory (VCRAM)

Data I/O pins for the SDRAM virtual connection memory (VCRAM)

Bank address pin for the SDRAM virtual connection memory (VCRAM)

DQM (data mask) pin for the SDRAM virtual conection memory (VCRAM)

RAS pin for the SDRAM virtual connection memory VCRAM)

CAS pin for the SDRAM virtual connection memory (VCRAM)

Write enable pin for the SDRAM virtual connection memory (VCRAM)

Common clock pin for both the CRAM and VCRAM memory arrays

Power supply pins

Ground Pins

FIG. 2 BLOCK DIAGRAM 512K x 32 SSRAM / 512K x 64

CADDR0-19

GCLK

CWE

COE

512K x 32 SBSRAM

ADDR0-17

CLK

GW

OE

DQ0-7

DQ8-15

DQ16-23

DQ24-31

VCADDR0-9

VCBS

VCDQM

VCRAS

VCCAS

VCWE

ADDR

BA

DQM0

DQM1

DQM2

DQM3

RAS

CAS

WE

CLK

256K x 32 x 2 SGRAM

DQ0-15

DQ16-31

VCDATA0-31

ADDR

BA

DQM0

DQM1

DQM2

DQM3

RAS

CAS

WE

CLK

256K x 32 x 2 SGRAM

DQ0-15

DQ16-31

VCDATA32-63

CDATA0-31

VCDATA0-63

White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com

2

July 2000 Rev. 0

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