CY7C1009-35DMB Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1009-35DMB Datasheet PDF : 11 Pages
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CY7C109
CY7C1009
128K x 8 Static RAM
Features
• High speed
— tAA = 10 ns
• Low active power
— 1017 mW (max., 12 ns)
• Low CMOS standby power
— 55 mW (max.), 4 mW (Low-power version)
• 2.0V Data Retention (Low-power version)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and OE options
Functional Description
The CY7C109 / CY7C1009 is a high-performance CMOS stat-
ic RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE1),
an active HIGH Chip Enable (CE2), an active LOW Output En-
able (OE), and three-state drivers. Writing to the device is ac-
complished by taking Chip Enable One (CE1) and Write En-
able (WE) inputs LOW and Chip Enable Two (CE2) input HIGH.
Data on the eight I/O pins (I/O0 through I/O7) is then written
into the location specified on the address pins (A0 through
A16).
Reading from the device is accomplished by taking Chip En-
able One (CE1) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).
The CY7C109 is available in standard 400-mil-wide SOJ and
32-pin TSOP type I packages. The CY7C1009 is available in
a 300-mil-wide SOJ package. The CY7C1009 and CY7C109
are functionally equivalent in all other respects.
Logic Block Diagram
Pin Configurations
SOJ
Top View
INPUT BUFFER
A0
A1
A2
A3
A4
A5
A6
512 x 256 x 8
ARRAY
A7
A8
CE1
CE2
COLUMN
DECODER
WE
OE
Selection Guide
POWER
DOWN
I/O0
I/O1
I/O2
I/O3
A11
A9
1
2
A8
3
I/O4 A13
WE
4
5
CE2
6
I/O5 A15
7
VCC
8
NC
9
I/O6 A16
10
A14
11
A12
12
I/O7 A7
13
A6
14
109–1
A5
A4
15
16
NC 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/O0 13
I/O1 14
I/O2 15
GND 16
32 VCC
31 A15
30 CE2
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE1
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3 109–2
TSOP I
Top View
(not to scale)
32 OE
31
A10
30 CE
29 I/O7
28 I/O6
27 I/O5
26 I/O4
25 I/O3
24 GND
23 I/O2
22 I/O1
21 I/O0
20 A0
19 A1
18 A2
17 A3
109–3
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Maximum CMOS Standby Current (mA)
Low-Power Version
Shaded areas contain preliminary information.
7C109-10
7C1009-10
10
195
10
2
7C109-12
7C1009-12
12
185
10
2
7C109-15
7C1009-15
15
155
10
2
7C109-20
7C1009-20
20
140
10
—
7C109-25
7C1009-25
25
135
10
—
7C109-35
7C1009-35
35
125
10
—
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
September 7, 1999
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