QL5632-33B-PQ208C Просмотр технического описания (PDF) - QuickLogic Corporation

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QL5632-33B-PQ208C

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

QL5632 Enhanced QuickPCI Device Data Sheet Rev. C

Signal

Usr_Write

Cfg_Write

Usr_Read

Cfg_Read

Cfg_RdData[31:0]

Usr_RdData[31:0]

Cfg_CmdReg3

Cfg_CmdReg4

Cfg_CmdReg6

Cfg_CmdReg8

Cfg_LatCnt[7:0]

Usr_MstRdAd_Sel

Usr_MstWrAd_Sel

Cfg_PERR_Det

Table 11: PCI Target Interface (Continued)

Type

Description

This signal is active throughout a "user write" transaction, which has been

decoded by Usr_WrDecode at the beginning of the transaction. The Write

O strobe for individual DWORDs of data (on Usr_Addr_WrData[31:0])

during a user Write transaction should be generated by logically ANDing

this signal with Usr_Adr_Inc.

This signal is active throughout a "configuration write" transaction. The

O

Write strobe for individual DWORDs of data (on Usr_Addr_WrData[31:0])

during a configuration Write transaction should be generated by logically

ANDing this signal with Usr_Adr_Inc.

O

This signal is active throughout a "user read" transaction, which has been

decoded by Usr_RdDecode at the beginning of the transaction.

O This signal is active throughout a "configuration read" transaction.

I

Data from the PCI configuration registers, required to be presented

during PCI configuration reads.

I

Data from the back-end user logic, required to be presented during PCI

user reads.

Bits 3 from the Command Register in the PCI configuration space (offset

I 04h). Enable Special Cycle monitoring. If high, the core reports data

parity error in Special Cycles through SERRN if Cfg_CmdReg8 is active.

Bits 4 from the Command Register in the PCI configuration space (offset

I

04h). Memory Write and Invalidate (MWI) Enable. If high, the core

generates MWI transactions as requested by the backend. Otherwise it

uses Memory Write instead even if MWI is requested.

Bits 6 from the Command Register in the PCI configuration space (offset

I 04h). Parity Error Response. If high, the core uses PERRN to report data

parity errors. Otherwise it never drives it.

Bits 8 from the Command Register in the PCI configuration space (offset

I 04h). SERRN Enable. If high, the cores uses SERRN to report address

parity errors if Cfg_CmdReg6 is high.

I

8-bit value of the Latency Timer in the PCI configuration space (offset

0Ch).

Used when a target read operation should return the value set on the

Mst_RdAd[31:0] pins. This select pin saves on logic which would

I otherwise need to be used to multiplex Mst_RdAd[31:0] into the

Usr_RdData[31:0] bus. When this signal is asserted, the data on

Usr_RdData[31:0] is ignored.

Used when a target read operation should return the value set on the

Mst_WrAd[31:0] pins. This select pin saves on logic which would

I otherwise need to be used to multiplex Mst_WrAd[31:0] into the

Usr_RdData[31:0] bus. When this signal is asserted, the data on

Usr_RdData[31:0] is ignored.

Parity error detected on the PCI bus. When this signal is active, bit 15 of

O the Status Register must be set in the PCI configuration space (offset

04h).

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