QL5632-33B-PQ208C Просмотр технического описания (PDF) - QuickLogic Corporation

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QL5632-33B-PQ208C

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

QL5632 Enhanced QuickPCI

Device Data Sheet

••••••

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic

and Dual Port SRAM

34

PCI Bus 33 MHz/32 bits (data and address)

Master

Controller

High

Speed

Data

Path

Target

Controller

32 bit Interface

Programmable

Logic

160 MHz

115/51 User I/O

FIFOs

High Speed

Logic Cells

PCI Bus

Config

space

DMA

Controller

Figure 1: QL5632 Diagram

Device Highlights

High Performance PCI Controller

• 32-bit / 33 MHz PCI Master/Target

• Zero-wait state PCI Master provides

132 MBps transfer rates

• Zero-wait-state PCI Target Write/One-wait-

state PCI Target Read interface

• Supports all PCI commands, including

configuration and MWI

• Supports fully-customizable byte enable for

master channels

• Target interface supports retry, disconnect

with/without data transfer, and target abort

• Fully programmable back-end interface

• Independent PCI bus (33 MHz) and local bus

(up to 160 MHz) clocks

• Fully customizable PCI Configuration Space

• Configurable FIFOs with depths up to 256

words

• Reference design with driver code (Win

95/98/Win 2000/NT4.0) available

• PCI v2.3 compliant

• Supports Type 0 Configuration Cycles in

Target mode

• 3.3 V PCI signaling

• 2.5 V Supply Voltage

• 280-ball LFBGA

• 208-pin PQFP

• Supports Extendable PCI functionality

• Unlimited/Continuous Burst Transfers

supported

Extendable PCI Functionality

• Support for PCI host-bridge function

• Support for Configuration Space from

0 × 40 to 0 × 3FF

• Multi-Function, Expanded Capabilities, and

Expansion ROM capable

• PCI v2.3 Power Management Spec

compatible

• PCI v2.3 Vital Product Data (VPD)

configuration support

Flexible Programmable Logic

• 772 Logic Cells

• 41,472 RAM bits

• Up to 115 I/O pins

• All back-end interface and glue-logic can be

implemented on chip

• Six 32-bit busses interface between the PCI

Controller and the Programmable Logic

• Eighteen 2,304 bit Dual Port High

Performance SRAM Blocks

• 1,889 flip-flops available

© 2003 QuickLogic Corporation

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www.quicklogic.com

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