ISPLSI2192VL-100LT128 Просмотр технического описания (PDF) - Lattice Semiconductor

Номер в каталоге

Компоненты Описание

производитель

ISPLSI2192VL-100LT128

2.5V In-System Programmable SuperFAST™ High Density PLD

Lattice Semiconductor 

Specifications ispLSI 2192VL

External Timing Parameters

Over Recommended Operating Conditions

PARAMETER

TEST 3

COND.

#

DESCRIPTION1

-150

-135

-100

UNITS

MIN. MAX. MIN. MAX. MIN. MAX.

tpd1

A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass — 6.0 — 7.5 — 10.0 ns

tpd2

A 2 Data Propagation Delay

— 8.5 — 10.0 — 13.0 ns

fmax

A

3 Clock Frequency with Internal Feedback 2

150 — 135 — 100 — MHz

fmax (Ext.)

fmax (Tog.)

—

4

Clock

Frequency

with

External

Feedback

(1

tsu2 +

) tco1

111

—

95

— 77

— MHz

— 5 Clock Frequency, Max. Toggle

166 — 143 — 100 — MHz

tsu1

— 6 GLB Reg. Setup Time before Clock, 4 PT Bypass 4.0 — 5.0 — 6.5 — ns

tco1

A 7 GLB Reg. Clock to Output Delay, ORP Bypass

— 4.0 — 4.5 — 5.0 ns

th1

— 8 GLB Reg. Hold Time after Clock, 4 PT Bypass

0.0 — 0.0 — 0.0 — ns

tsu2

— 9 GLB Reg. Setup Time before Clock

5.0 — 6.0 — 8.0 — ns

tco2

A 10 GLB Reg. Clock to Output Delay

— 5.0 — 5.5 — 6.0 ns

th2

— 11 GLB Reg. Hold Time after Clock

0.0 — 0.0 — 0.0 — ns

tr1

A 12 Ext. Reset Pin to Output Delay, ORP Bypass

— 6.0 — 8.0 — 13.5 ns

trw1

— 13 Ext. Reset Pulse Duration

5.0 — 5.5 — 6.5 — ns

tptoeen

B 14 Input to Output Enable

— 10.0 — 12.0 — 15.0 ns

tptoedis

C 15 Input to Output Disable

— 10.0 — 12.0 — 15.0 ns

tgoeen

B 16 Global OE Output Enable

— 6.0 — 7.0 — 9.0 ns

tgoedis

C 17 Global OE Output Disable

— 6.0 — 7.0 — 9.0 ns

twh

— 18 External Synchronous Clock Pulse Duration, High 3.0 — 3.5 — 5.0 — ns

twl

— 19 External Synchronous Clock Pulse Duration, Low 3.0 — 3.5 — 5.0 — ns

1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.

2. Standard 16-bit counter using GRP feedback.

3. Reference Switching Test Conditions section.

Table 2-0030C/2192VL

5

Share Link: