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IDT72V81L15PAG

3.3 Volt CMOS DUAL ASYNCHRONOUS FIFO

Integrated Device Technology 

IDT72V81/72V82/72V83/72V84/72V85 3.3V CMOS DUAL ASYNCHRONOUS FIFO

512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9

COMMERCIAL TEMPERATURE RANGE

LAST READ

IGNORED

READ

FIRST WRITE

ADDITIONAL FIRST READ

WRITES

W

R

EF

DATA OUT

tREF

tA

VALID

tWEF

Figure 5. Empty Flag From Last Read to First Write

VALID

3966 drw 07

RT

W,R

HF, EF, FF

tRTC

tRT

tRTS

tRTF

Figure 6. Retransmit

tRTR

FLAG VALID

3966 drw 08

W

tWEF

EF

tRPE

R

3966 drw 09

Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse

R

tRFF

FF

tWPF

W

3966 drw 10

Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse

6

JULY 17, 2006

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