ICS9112M-17-T Просмотр технического описания (PDF) - Integrated Circuit Systems

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ICS9112M-17-T

Low Skew Output Buffer

Integrated Circuit Systems 

ICS9112-17

Application Suggestion:

ICS9112-17 is a mixed analog/digital product. The analog portion of the PLL is very sensitive to any random noise generated

by charging or discharging of internal or external capacitor on the power supply pins. This type of noise will cause excess

jitter to the outputs of ICS9112-17. Below is a recommended lay out to alleviate any addition noise. For additional

information on FT. layout, please refer to our AN07. The 0.1 uF capacitors should be connected as close as possible to power

pins (4 & 13). An Isolated power plane with a 2.2 uF capacitor to ground will enhance the power line stability.

0.1µF

1 REF

33Ω

2 CLKA1

33Ω

3 CLKA2

4 VDD

5 GND

33Ω

6 CLKB1

33Ω

7 CLKB2

10KΩ

8 FS2

GND

VDD

33Ω

CLKOUT 16

33Ω

CLKA4 15

33Ω

CLKA3 14

VDD 13

GND 12

33Ω

CLKB4 11

33Ω

CLKB3 10

FS1 9

10KΩ

GND

VDD

0.1µF

6

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