HD6417708RF100 Просмотр технического описания (PDF) - Renesas Electronics
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HD6417708RF100 Datasheet PDF : 633 Pages
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17.3.4 Basic Timing ........................................................................................................ 512
17.3.5 Burst ROM Timing .............................................................................................. 515
17.3.6 DRAM Timing ..................................................................................................... 518
17.3.7 Synchronous DRAM Timing................................................................................ 528
17.3.8 Pseudo-SRAM Timing ......................................................................................... 539
17.3.9 PCMCIA Timing.................................................................................................. 544
17.3.10 Peripheral Module Signal Timing ........................................................................ 551
17.3.11 AC Characteristics Test Conditions ..................................................................... 554
Appendix A Pin Functions ................................................................................................ 555
A.1 Pin States ........................................................................................................................... 555
A.2 Pin Specifications .............................................................................................................. 558
A.3 Handling of Unused Pins ................................................................................................... 561
A.4 Pin States in Access to Each Address Space ..................................................................... 562
Appendix B Control Registers ......................................................................................... 598
B.1 Register Address Map........................................................................................................ 598
B.2 Register Bit List................................................................................................................. 602
B.3 Register States in Reset and Power-Down States.............................................................. 608
Appendix C Delay Time Variation Due to Load Capacitance ............................... 612
Appendix D Package Dimensions................................................................................... 613
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