MC74AC257DR2G Просмотр технического описания (PDF) - ON Semiconductor
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MC74AC257DR2G Datasheet PDF : 9 Pages
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MC74AC257, MC74ACT257
PIN NAME
PIN
S
OE
I0a−I0d
I1a−I1d
Za−Zd
FUNCTION
Common Data Select Input
3−State Output Enable Input
Data Inputs from Source 0
Data Inputs from Source 1
3−State Multiplexer Outputs
TRUTH TABLE
Output
Enable
Select
Input
OE
S
H
X
L
H
L
H
L
L
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Data
Inputs
I0
I1
X
X
X
L
X
H
L
X
H
X
Outputs
Z
Z
L
H
L
H
OE I0a I1a I0b I1b I0c I1c I0d I1d
S
Za
Zb
Zc
Zd
FUNCTIONAL DESCRIPTION
The MC74AC257/74ACT257 is a quad 2−input
multiplexer with 3−state outputs. It selects four bits of data
from two sources under control of a Common Data Select
input. When the Select input is LOW, the I0x inputs are
selected and when Select is HIGH, the I1x inputs are
selected. The data on the selected inputs appears at the
outputs in true (noninverted) form. The device is the logic
implementation of a 4−pole, 2−position switch where the
position of the switch is determined by the logic levels
supplied to the Select input. The logic equations for the
outputs are shown below:
Za = OE•(I1a•S+I0a•S)
Zb = OE•(I1b•S+I0b•S)
Zc = OE•(I1c•S+I0c•S)
Zd = OE•(I1d•S+I0d•S)
When the Output Enable input (OE) is HIGH, the outputs
are forced to a high impedance state. If the outputs are tied
together, all but one device must be in the high impedance
state to avoid high currents that would exceed the maximum
ratings. Designers should ensure the Output Enable signals
to 3−state devices whose outputs are tied together are
designed so there is no overlap.
Figure 2. Logic Symbol
OE
I0a
I1a
I0b
I1b
I0c
I1c
I0d
I1d
S
NOTE:
Za
Zb
Zc
Zd
This diagram is provided only for the understanding of logic operations
and should not be used to estimate propagation delays.
Figure 3. Logic Diagram
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