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Компоненты Описание

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W83877TD

WINBOND I/O

Winbond 

W83877TF/W83877TG

6.2.5

6.2.6

6.2.7

6.2.8

6.2.9

UART FIFO Control Register (UFR) (Write only)....................................................................42

Interrupt Status Register (ISR) (Read only) ............................................................................43

Interrupt Control Register (ICR) (Read/Write).........................................................................44

Programmable Baud Generator (BLL/BHL) (Read/Write).......................................................44

User-defined Register (UDR) (Read/Write) ............................................................................45

7. PARALLEL PORT ......................................................................................................................... 46

7.1 Printer Interface Logic ........................................................................................................... 46

7.2 Enhanced Parallel Port (EPP)............................................................................................... 48

7.2.1 Data Swapper.........................................................................................................................48

7.2.2 Printer Status Buffer ...............................................................................................................48

7.2.3 Printer Control Latch and Printer Control Swapper.................................................................49

7.2.4 EPP Address Port...................................................................................................................49

7.2.5 EPP Data Port 0-3 ..................................................................................................................50

7.2.6 Bit Map of Parallel Port and EPP Registers............................................................................50

7.2.7 EPP Pin Descriptions .............................................................................................................51

7.2.8 EPP Operation .......................................................................................................................51

7.3 Extended Capabilities Parallel (ECP) Port............................................................................ 52

7.3.1 ECP Register and Mode Definitions .......................................................................................52

7.3.2 Data and ecpAFifo Port ..........................................................................................................53

7.3.3 Device Status Register (DSR) ................................................................................................53

7.3.4 Device Control Register (DCR)...............................................................................................54

7.3.5 cFifo (Parallel Port Data FIFO) Mode = 010 ...........................................................................54

7.3.6 ecpDFifo (ECP Data FIFO) Mode = 011.................................................................................54

7.3.7 tFifo (Test FIFO Mode) Mode = 110 .......................................................................................55

7.3.8 cnfgA (Configuration Register A) Mode = 111 ........................................................................55

7.3.9 cnfgB (Configuration Register B) Mode = 111 ........................................................................55

7.3.10 ecr (Extended Control Register) Mode = all............................................................................56

7.3.11 Bit Map of ECP Port Registers ...............................................................................................57

7.3.12 ECP Pin Descriptions .............................................................................................................58

7.3.13 ECP Operation .......................................................................................................................59

7.3.14 FIFO Operation ......................................................................................................................59

7.3.15 DMA Transfers .......................................................................................................................60

7.3.16 Programmed I/O (NON-DMA) Mode.......................................................................................60

7.4 Extension FDD Mode (EXTFDD) .......................................................................................... 60

7.5 Extension 2FDD Mode (EXT2FDD) ...................................................................................... 60

8. PLUG AND PLAY CONFIGURATION ........................................................................................... 61

9. ACPI /LEGACY FEATURE AND AUTO POWER MANAGEMENT ............................................... 61

9.1 ACPI/Legacy power management ........................................................................................ 61

9.2 Device(auto) power management......................................................................................... 61

Publication Release Date: May 2006

-III-

Revision 0.7

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