W83977TF-A Просмотр технического описания (PDF) - Winbond
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W83977TF-A Datasheet PDF : 160 Pages
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W83977TF
11.1 CHIP (GLOBAL) CONTROL REGISTER ..............................................................................................96
11.2 LOGICAL DEVICE 0 (FDC)...................................................................................................................100
11.3 LOGICAL DEVICE 1 (PARALLEL PORT)..........................................................................................103
11.4 LOGICAL DEVICE 2 (UART A)¢) ........................................................................................................104
11.5 LOGICAL DEVICE 3 (UART B) ...........................................................................................................104
11.6 LOGICAL DEVICE 5 (KBC) ..................................................................................................................106
11.7 LOGICAL DEVICE 7 (GP I/O PORT I).................................................................................................107
11.8 LOGICAL DEVICE 8 (GP I/O PORT II) ...............................................................................................110
11.9 LOGICAL DEVICE 9 (GP I/O PORT III) ..............................................................................................114
11.10 LOGICAL DEVICE A (ACPI) ................................................................................................................117
12. SPECIFICATIONS ............................................................................................................123
12.1 ABSOLUTE MAXIMUM RATINGS ....................................................................................................123
12.2 DC CHARACTERISTICS .......................................................................................................................123
12.3 AC CHARACTERISTICS .......................................................................................................................127
12.3.1 FDC: DATA RATE = 1 MB, 500 KB, 300 KB, 250 KB/SEC...............................................127
12.3.2 UART/PARALLEL PORT........................................................................................................129
12.3.3 PARALLEL PORT MODE PARAMETERS ..........................................................................129
12.3.4 EPP DATA OR ADDRESS READ CYCLE TIMING PARAMETERS..............................130
12.3.5 EPP DATA OR ADDRESS WRITE CYCLE TIMING PARAMETERS ............................131
12.3.6 PARALLEL PORT FIFO TIMING PARAMETERS..............................................................132
12.3.7 ECP PARALLEL PORT FORWARD TIMING PARAMETERS.........................................132
12.3.8 ECP PARALLEL PORT REVERSE TIMING PARAMETERS ...........................................132
12.3.9 KBC TIMING PARAMETERS ................................................................................................133
12.3.10 GPIO TIMING PARAMETERS................................................................................................134
13. TIMING WAVEFORMS ..................................................................................................135
13.1 FDC ............................................................................................................................................................135
13.2 UART/PARALLEL...................................................................................................................................136
13.2.1 MODEM CONTROL TIMING ................................................................................................137
13.3 PARALLEL PORT ...................................................................................................................................138
13.3.1 PARALLEL PORT TIMING.....................................................................................................138
13.3.2 EPP DATA OR ADDRESS READ CYCLE (EPP VERSION 1.9)......................................139
13.3.3 EPP DATA OR ADDRESS WRITE CYCLE (EPP VERSION 1.9) ....................................140
13.3.4 EPP DATA OR ADDRESS READ CYCLE (EPP VERSION 1.7)......................................141
13.3.5 EPP DATA OR ADDRESS WRITE CYCLE (EPP VERSION 1.7) ....................................142
13.3.6 PARALLEL PORT FIFO TIMING...........................................................................................142
Publication Release Date: March 1998
-V-
Revision 0.62
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