LH5420
256 × 36 × 2 Bidirectional FIFO
FEATURES
• Fast Cycle Times: 25/30/35 ns
• Two 256 × 36-bit FIFO Buffers
• Full 36-bit Word Width
• Selectable 36/18/9-bit Word Width
on Port B
• Independently-Synchronized (‘Fully
Asynchronous’) Operation of Port A and
Port B
• ‘Synchronous’ Enable-Plus-Clock Control
at Both Ports
• R/W, Enable, Request, and Address
Control Inputs are Sampled on the Rising
Clock Edge
• Synchronous Request/Acknowledge
‘Handshake’ Capability; Use is Optional
• Device Comes Up Into a Known Default
State at Reset; Programming is Allowed,
but is not Required
• Asynchronous Output Enables
• Five Status Flags per Port: Full,
Almost-Full, Half-Full, Almost-Empty, and
Empty
• Almost-Full Flag and Almost-Empty Flag
are Programmable
• Mailbox Registers with
Synchronized Flags
• Data-Bypass Function
• Data-Retransmit Function
• Automatic Byte Parity Checking
* For PQFP-to-PGA conversion for thru-hole board designs, Sharp
recommends ITT Pomona Electronics’ SMT/PGA Generic Con-
verter model #5853®. This converter maps the LH543620 132-
pin PQFP to a generic 13 × 13, 132-pin PGA (100-mil pitch). For
more information, contact Sharp or ITT Pomona Electronics at
1500 East Ninth Street, Pomona, CA 91766, (909) 469-2900.
• TTL/CMOS-Compatible I/O
• Space-Saving PQFP Package
• PQFP to PGA Package Conversion *
FUNCTIONAL DESCRIPTION
The LH5420 contains two FIFO buffers, FIFO #1 and
FIFO #2. These operate in parallel, but in opposite direc-
tions, for bidirectional data buffering. FIFO #1 and FIFO
#2 each are organized as 256 words by 36 bits. The
LH5420 is ideal either for wide unidirectional applications
or for bidirectional data applications; component count
and board area are reduced.
The LH5420 has two 36-bit ports, Port A and Port B.
Each port has its own port-synchronous clock, but the two
ports may operate asynchronously relative to each other.
Data flow is initiated at a port by the rising edge of the
appropriate clock; it is gated by the corresponding edge-
sampled enable, request, and read/write control signals.
At the maximum operating frequency, the clock duty cycle
may vary from 40% to 60%. At lower frequencies, the
clock waveform may be quite asymmetric, as long as the
minimum pulse-width conditions for clock-HIGH and
clock-LOW remain satisfied; the LH5420 is a fully-static
part.
Conceptually, the port clocks CKA and CKB are free-
running, periodic ‘clock’ waveforms, used to control other
signals which are edge-sampled. However, there actually
is not any absolute requirement that these ‘clock’ wave-
forms must be periodic. An ‘asynchronous’ mode of
operation is possible, in one or both directions, inde-
pendently, if the appropriate enable and request inputs
are continuously asserted, and enough aperiodic ‘clock’
pulses of suitable duration are generated by external logic
to cause all necessary actions to occur.
A synchronous request/acknowledge handshake
facility is provided at each port for FIFO data access. This
request/ acknowledge handshake resolves FIFO full and
empty boundary conditions, when the two ports are oper-
ated asynchronously relative to each other.
FIFO status flags monitor the extent to which each
FIFO buffer has been filled. Full, Almost-Full, Half-Full,
Almost-Empty, and Empty flags are included for each
FIFO. The Almost-Full and Almost-Empty flags are pro-
grammable over the entire FIFO depth, but are automat-
ically initialized to eight locations from the respective FIFO
boundaries at reset. A data block of 256 or fewer words
may be retransmitted any desired number of times.
Two mailbox registers provide a separate path for
passing control words or status words between ports.
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