CY62128EV30(2007) Просмотр технического описания (PDF) - Cypress Semiconductor
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CY62128EV30 Datasheet PDF : 11 Pages
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CY62128EV30 MoBL®
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature .................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................... 55°C to +125°C
Supply Voltage to Ground
Potential ......................................... –0.3V to VCC(max) + 0.3V
DC Voltage Applied to Outputs
in High-Z State[4, 5]......................... –0.3V to VCC(max) + 0.3V
DC Input Voltage[4,5] ...................... –0.3V to VCC(max) + 0.3V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch up Current..................................................... > 200 mA
Operating Range
Device
CY62128EV30LL
Range
Ind’l/Auto-A
Auto-E
Ambient
Temperature
VCC[6]
–40°C to +85°C 2.2V to
–40°C to +125°C 3.6V
Electrical Characteristics (Over the Operating Range)
Parameter
Description
VOH
Output HIGH Voltage
Test Conditions
IOH = –0.1 mA
IOH = –1.0 mA, VCC > 2.70V
45 ns (Ind’l/Auto-A)
Min Typ[3] Max
2.0
2.4
55 ns (Auto-E)
Min Typ[3] Max Unit
2.0
V
2.4
V
VOL
VIH
VIL
IIX
IOZ
ICC
ISB1
ISB2[7]
Output LOW Voltage IOL = 0.1 mA
IOL = 2.1 mA, VCC > 2.70V
Input HIGH Voltage
VCC = 2.2V to 2.7V
1.8
VCC= 2.7V to 3.6V
2.2
Input LOW Voltage
VCC = 2.2V to 2.7V
VCC= 2.7V to 3.6V
Input Leakage Current GND < VI < VCC
Output Leakage Current GND < VO < VCC, Output Disabled
VCC Operating Supply
Current
f = fmax = 1/tRC VCC = VCCmax
f = 1 MHz
IOUT = 0 mA
CMOS levels
Automatic CE
CE1 > VCC−0.2V, CE2 < 0.2V
Power down
VIN > VCC–0.2V, VIN < 0.2V)
Current — CMOS Inputs f = fmax (Address and Data Only),
f = 0 (OE and WE), VCC = 3.60V
Automatic CE
CE1 > VCC – 0.2V, CE2 < 0.2V
Power down
VIN > VCC – 0.2V or VIN < 0.2V,
Current — CMOS Inputs f = 0, VCC = 3.60V
–0.3
–0.3
–1
–1
0.4
0.4
VCC + 1.8
0.3V
VCC + 2.2
0.3V
0.6 –0.3
0.8 –0.3
+1
–4
+1
–4
11 16
1.3 2.0
1
4
1
4
0.4 V
0.4 V
VCC + V
0.3V
VCC + V
0.3V
0.6 V
0.8 V
+4 µA
+4 µA
11 35 mA
1.3 4.0 mA
1
35 µA
1
30 µA
Capacitance (For all packages)[8]
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = VCC(typ)
Max
Unit
10
pF
10
pF
Notes:
4. VIL(min) = –2.0V for pulse durations less than 20 ns.
5. VIH(max) = VCC+0.75V for pulse durations less than 20 ns.
6. Full device AC operation assumes a 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization.
7. Only chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
8. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05579 Rev. *C
Page 3 of 11
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