CY62128EV30(2007) Просмотр технического описания (PDF) - Cypress Semiconductor

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CY62128EV30
(Rev.:2007)

1 Mbit (128K x 8) Static RAM

Cypress Semiconductor 

CY62128EV30 MoBL®

Switching Waveforms

Read Cycle 1 (Address transition controlled) [15, 16]

tRRCC

ADDRESS

tAA

tOHA

DATA OUT

PREVIOUS DATA VALID

Read Cycle No. 2 (OE controlled) [10, 16, 17]

ADDRESS

CE

OE

DATA OUT

VCC

SUPPLY

CURRENT

tACE

tDOE

tLZOE

HIGH IMPEDANCE

tLZCE

tPU

50%

Write Cycle No. 1 (WE controlled) [10, 15, 18, 19]

ADDRESS

CE

tRC

tWC

tSCE

DATA VALID

tAW

tSA

tPWE

WE

DATA VALID

tHZOE

tHZCE

HIGH

IMPEDANCE

tPD

ICC

50%

ISB

tHA

OE

DATA IO

NOTE 20

tHZOE

tSD

tHD

DATA VALID

Notes:

15. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.

16. WE is HIGH for read cycle.

17. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH.

18. Data IO is high impedance if OE = VIH.

19. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state.

20. During this period, the IOs are in output state. Do not apply input signals.

Document #: 38-05579 Rev. *C

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