CY8C27143-24PXI Просмотр технического описания (PDF) - Cypress Semiconductor
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CY8C27143-24PXI Datasheet PDF : 53 Pages
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CY8C27143, CY8C27243
CY8C27443, CY8C27543, CY8C27643
Pinouts
The CY8C27x43 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port
pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.
8-Pin Part Pinout
Table 3. Pin Definitions - 8-Pin PDIP
Pin
Type
Pin
No. Digital Analog Name
Description
1
IO
IO
P0[5] Analog column mux input and column output.
2
IO
IO
P0[3] Analog column mux input and column output.
3
IO
P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK*.
Figure 3. CY8C27143 8-Pin PSoC Device
A, IO,P0[5]
A,IO, P0[3]
I2 CSCL ,XTAL in , P1 [1 ]
Vss
18
2PDIP 7
36
45
Vdd
P0[4], A,IO
P0[2], A,IO
P1[0],XTALout,I2CSDA
4
Power
Vss Ground connection.
5
IO
P1[0] Crystal Output (XTALout), I2C Serial Data (SDA),
ISSP-SDATA*.
6
IO
IO
P0[2] Analog column mux input and column output.
7
IO
IO
P0[4] Analog column mux input and column output.
8
Power
Vdd Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference
Manual for details.
20-Pin Part Pinout
Table 4. Pin Definitions - 20-Pin SSOP, SOIC
Pin
Type
Pin
No. Digital Analog Name
Description
1
IO
I
P0[7] Analog column mux input.
2
IO
IO
P0[5] Analog column mux input and column output.
3
IO
IO
P0[3] Analog column mux input and column output.
4
IO
I
P0[1] Analog column mux input.
5
Power
SMP Switch Mode Pump (SMP) connection to external
components required.
6
IO
P1[7] I2C Serial Clock (SCL).
7
IO
P1[5] I2C Serial Data (SDA).
8
IO
P1[3]
9
IO
P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK*.
10
Power
Vss Ground connection.
11
IO
P1[0] Crystal Output (XTALout), I2C Serial Data (SDA),
ISSP-SDATA*.
12
IO
P1[2]
13
IO
P1[4] Optional External Clock Input (EXTCLK).
14
IO
P1[6]
15
Input
XRES Active high external reset with internal pull down.
16
IO
I
P0[0] Analog column mux input.
17
IO
IO
P0[2] Analog column mux input and column output.
18
IO
IO
P0[4] Analog column mux input and column output.
19
IO
I
P0[6] Analog column mux input.
20
Power
Vdd Supply voltage.
Figure 4. CY8C27243 20-Pin PSoC Device
A, I,P0[7] 1
A,IO, P0[5] 2
A,IO, P0[3] 3
A,I, P0[1] 4
SMP 5
I2CSCL,P1[7] 6
I2CSDA,P1[5] 7
P1[3] 8
I2CSCL,XTALin,P1[1] 9
Vss 10
20
19
18
17
SSOP 16
SOIC 15
14
13
12
11
Vdd
P0[6], A,I
P0[4], A,IO
P0[2], A,IO
P0[0], A,I
XRES
P1[6]
P1[4],EXTCLK
P1[2]
P1[0],XTALout,I2CSDA
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 38-12012 Rev. *M
Page 8 of 53
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