CY7C1041BNV33L-12ZXC Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1041BNV33L-12ZXC Datasheet PDF : 8 Pages
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CY7C1041BNV33
Switching Characteristics[4] Over the Operating Range
Parameter
Description
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Low Z
OE HIGH to High Z[5, 6]
CE LOW to Low Z[6]
CE HIGH to High Z[5, 6]
tPU
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
tDBE
Byte Enable to Data Valid
tLZBE
Byte Enable to Low Z
tHZBE
Byte Disable to High Z
WRITE CYCLE[7, 8]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
tBW
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[6]
WE LOW to High Z[5, 6]
Byte Enable to End of Write
-12
-15
Min.
Max.
Min.
Max.
Unit
12
15
ns
12
15
ns
3
3
ns
12
15
ns
6
7
ns
0
0
ns
6
7
ns
3
3
ns
6
7
ns
0
0
ns
12
15
ns
6
7
ns
0
0
ns
6
7
ns
12
15
ns
10
12
ns
10
12
ns
0
0
ns
0
0
ns
10
12
ns
7
8
ns
0
0
ns
3
3
ns
6
7
ns
10
12
ns
Data Retention Characteristics Over the Operating Range (For L version only)
Parameter
Description
Conditions[10]
Min.
Max.
Unit
VDR
VCC for Data Retention
2.0
V
ICCDR
tCDR[3]
Data Retention Current
VCC = VDR = 2.0V,
Chip Deselect to Data
Retention Time
CE > VCC – 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
0
330
µA
ns
tR[9]
Operation Recovery Time
tRC
ns
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of
either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
9. tr < 3 ns for the -12 and -15 speeds.
10. No input may exceed VCC + 0.5V.
Document #: 001-06434 Rev. **
Page 3 of 8
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