CY23S08(2004) Просмотр технического описания (PDF) - Cypress Semiconductor

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CY23S08
(Rev.:2004)

3.3V Zero Delay Buffer

Cypress Semiconductor 

PRELIMINARY

CY23S08

Table 1. Select Input Decoding

S2

S1

CLOCK A1–A4

0

0

Three-State

0

1

Driven

1

0

Driven

1

1

Driven

Table 2. Available CY23S08 Configurations

CLOCK B1–B4

Three-State

Three-State

Driven

Driven

Output Source

PLL

PLL

Reference

PLL

PLL Shutdown

Y

N

Y

N

Device

Feedback From

Bank A Frequency

Bank B Frequency

CY23S08–1

Bank A or Bank B

Reference

Reference

CY23S08–1H

Bank A or Bank B

Reference

Reference

CY23S08–2

Bank A

Reference

Reference/2

CY23S08–2H

Bank A

Reference

Reference/2

CY23S08–2

Bank B

2 X Reference

Reference

CY23S08–2H

CY23S08–3

Bank B

Bank A

2 X Reference

2 X Reference

Reference

Reference or Reference[1]

CY23S08–3

Bank B

4 X Reference

2 X Reference

CY23S08–4

Bank A or Bank B

2 X Reference

2 X Reference

Pin Description

Pin

Signal

1

REF[2]

2

CLKA1[3]

3

CLKA2[3]

Description

Input reference frequency, 5V tolerant input

Clock output, Bank A

Clock output, Bank A

4

VDD

5

GND

6

CLKB1[3]

7

CLKB2[3]

8

S2[4]

9

S1[4]

10

CLKB3[3]

11

CLKB4[3]

3.3V supply

Ground

Clock output, Bank B

Clock output, Bank B

Select input, bit 2

Select input, bit 1

Clock output, Bank B

Clock output, Bank B

12

GND

Ground

13

VDD

14

CLKA3[3]

15

CLKA4[3]

3.3V supply

Clock output, Bank A

Clock output, Bank A

16

FBK

PLL feedback input

Spread Aware™

Many systems being designed now utilize a technology called

Spread Spectrum Frequency Timing Generation. Cypress has

been one of the pioneers of SSFTG development, and we

designed this product so as not to filter off the Spread

Spectrum feature of the Reference input, assuming it exists.

When a zero delay buffer is not designed to pass the SS

feature through, the result is a significant amount of tracking

skew which may cause problems in systems requiring

synchronization.

For more details on Spread Spectrum timing technology,

please see Cypress’s application note EMI Suppression

Techniques with Spread Spectrum Frequency Timing

Generator (SSFTG) ICs.

Notes:

1. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the CY23S08–2.

2. Weak pull-down.

3. Weak pull-down on all outputs.

4. Weak pull-ups on these inputs.

Document #: 38-07265 Rev. *D

Page 2 of 8

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